Memory data transfer method and system
View Patent ↗A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from each of the contiguous first locations is retrieved and stored in a corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. The DMA process is performed absent retrieving the same data a second other time prior to storing of same within the corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations.
1. A method for improving efficiency of a cryptographic process performed by two or more processors comprising:
moving a first data, using Direct Memory Access (DMA) capability, from a memory buffer to two or more processing engine memory buffers each coupled with one of said processors in response to an initial command;
executing one or more cryptographic processes on a first one of said processor on the first data located in the processing engine memory buffer coupled with the first one of said processors to generate a second data;
storing the second data in the processing engine memory buffer couples to the first one of said processors;
executing one or more processes on a second one of said processors on the first data located in the processing engine memory buffer coupled with the second one of said processors to generate a third data;
storing the third data in a first output buffer;
transferring the second data from the processing engine memory buffer coupled to the first one of said processors to a second output buffer.
2. The method according to claim 1 wherein said first processor is a cryptographic engine and said second processor is a hashing engine.
3. The method according to claim 1 wherein the DMA process is initiated with a single command.
4. The method according to claim 1 wherein the DMA process is initiated with from one to three commands.
5. An improved cryptographic circuit comprising:
two or more processors;
two or more processing engine memory buffers each coupled with one of said two or more processors;
a DMA (Direct Memory Access) transfer circuit configured for, in response to a command, moving a first data from a memory buffer to two or more processing engine memory buffers;
a first one of said processors executing one or more cryptographic processes on the first data to generate a second data and storing the second data in the processing engine memory buffer coupled with said first one of said processor;
a second one of said processors executing one or more processes on the first data to generate a third data and storing the third data in a first output buffer; and
said first one of said processors transferring the second data to a second output buffer.
6. The circuit according to claim 5 wherein said first processor is a cryptographic engine and said second processor is a hashing engine.
7. The method according to claim 1 wherein said moving the first data to two or more processing engine is done simultaneously.
8. The method according to claim 1 wherein said processing engine memory buffer is a circular buffer.
9. The method according to claim 1 wherein said transferring is done prior to moving new data into said memory buffer.
10. The circuit according to claim 5 wherein said DMA transfer circuit moves the first data to two or more processing engine is done simultaneously.
11. The circuit according to claim 5 wherein said processing engine memory buffer is a circular buffer.
12. The circuit according to claim 5 wherein said one of said processor transfers the third data to an output buffer prior to moving new data into said memory buffer.