Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
1. An apparatus comprising:
an array of memory cells in a package;
volatile memory configured to store defective address data responsive to entering a soft post-package repair mode;
non-volatile memory configured to store other defective address data;
a match logic circuit configured to generate a match signal indicating whether address data corresponding to an address of the array to be accessed matches the defective address data stored in the volatile memory; and
a decoder configured to select a first portion of the memory cells of the array to be accessed instead of a second portion of the memory cells of the array responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory, wherein the second portion of the memory cells of the array corresponds to a replacement address for the address of the array to be accessed associated with the other defective address data stored in the non-volatile memory.
2. The apparatus of claim 1 , wherein the decoder is configured to select the second portion of the memory cells of the array to be accessed responsive to:
the match signal indicating that the address data corresponding to the address to be accessed does not match the defective address data stored in the volatile memory; and
another match signal indicating that the address data corresponding to the address to be accessed matches the other defective address data stored in the non-volatile memory of the apparatus.
3. The apparatus of claim 1 , wherein the decoder is further configured to prevent the second portion of the memory cells of the array from being selected responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the detective address data stored in the volatile memory.
4. The apparatus of claim 1 , wherein the apparatus is a memory device, the memory device comprising a mode register, wherein the memory device is configured to enter the soft post package repair mode responsive to a change in a value stored in the mode register.
5. The apparatus of claim 1 , wherein the apparatus comprises a plurality of memory banks, wherein a memory bank of the plurality of memory banks includes the memory cells, the volatile memory, the match logic circuit, and the decoder.
6. The apparatus of claim 5 , wherein the apparatus is configured to perform soft post package repair on a bank by bank basis.
7. The apparatus of claim 1 , wherein the volatile memory is configured to store the defective address data responsive to receiving an activate command after entering the soft post package repair mode.
8. The apparatus of claim 1 , further comprising a control logic circuit configured to assert a pulse signal responsive to entering the soft post package repair mode and receiving an activate signal, wherein the volatile memory is configured to store the defective address data responsive to the pulse signal being asserted.
9. The apparatus of claim 1 , wherein the memory cells are included in at least one of a dynamic random access memory device or a static random access memory device.
10. The apparatus of claim 1 , further comprising a controller external to the package and in communication with nodes of the package, wherein the controller is configured to cause the soft post package repair mode to be entered.
11. The apparatus of claim 10 , wherein the apparatus comprises a plurality of memory devices comprising a first memory device and a second memory device, wherein the first memory device comprises the memory cells and the volatile memory, and wherein the controller is configured to retrieve the defective address data from non-volatile memory of the second memory device and provide the defective address data to the first memory device.
12. The apparatus of claim 11 , wherein the apparatus comprises a packaged unit that comprises the plurality of memory devices, wherein the packaged unit comprises at least one of a dual inline memory module or a memory card.
13. The apparatus of claim 1 , wherein the non-volatile memory comprises at least one of a fuse or an antifuse.
14. The apparatus of claim 1 , wherein each of the first and second portions of memory cells of the array comprise redundant memory cells of the array of a memory device.
15. An electronically-implemented method for post-package repair of a packaged memory device, the method comprising:
storing defective address data in volatile memory of the packaged memory device, the defective address data corresponding to an address mapped to a defective portion of memory cells of the memory device;
generating a match signal responsive to a comparison of the defective address data with received address data; and
responsive to the match signal indicating that the defective address data and the received address data match,
remapping the received address data to a first portion of memory cells of the memory device instead of a second portion of memory cells of the memory device, wherein the second portion of memory cells corresponds to a replacement address associated with other defective address data stored in non-volatile memory associated with the memory device.
16. The method of claim 15 , further comprising storing the other defective address data in the non-volatile memory in a post package repair operation.
17. The method of claim 15 , wherein the other defective address data was stored in the nonvolatile memory prior to packaging the packaged memory device.
18. The method of claim 15 , further comprising retrieving the other defective data from a second memory device that is separate from the packaged memory device.
19. The method of claim 15 , wherein remapping comprises remapping the address to a particular row of redundant memory cells of the packaged memory device.
20. The method of claim 15 , further comprising storing the defective address data in the volatile memory responsive to powering up the packaged memory device.
21. A memory device comprising:
a memory array in a package;
volatile memory in the package, the volatile memory configured to store defective address data received at an externally accessible node of the package responsive to a soft post-package repair mode being entered and an activate command being received; and
a decoder in the package, the decoder configured to select a group of redundant memory cells of the memory array responsive to received address data matching the defective address data stored in the volatile memory.
22. The memory device of claim 21 , wherein the decoder is further configured to prevent another group of redundant memory cells of the memory array from being selected responsive to the received address data matching the defective address data stored in the volatile memory.
23. The memory device of claim 21 , further comprising programmable elements, wherein the decoder is further configured to map the received address to another group of redundant memory cells of the memory array responsive to data stored in the programmable elements if the received address data does not match the defective address data stored in the volatile memory.
24. The memory device of claim 23 , wherein the programmable elements comprise antifuses.
25. The apparatus of claim 1 , wherein the decoder is configured to override any replacement address stored in non-volatile memory responsive to the match signal indicates that the address data matches the defective address data stored in the volatile memory.