Semiconductor device
This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.
1. A semiconductor device comprising:
a wiring substrate having a first insulating layer having a first main surface and a second main surface opposite the first main surface, a solder resist layer formed over the first main surface of the first insulating layer, a plurality of through-hole wiring portions which penetrate the first main surface to the second main surface of the first insulating layer, and a plurality of wirings formed over the first main surface of the first insulating layer and electrically connected to the plurality of through-hole wiring portions, respectively, wherein parts of the plurality of through-hole wiring portions disposed over the first main surface of the first insulating layer are covered with the solder resist layer; and
a semiconductor chip having an obverse surface over which a plurality of electrode pads are formed and a reverse surface opposite the obverse surface,
wherein a plurality of openings are formed in the solder resist layer such that a part of each of the plurality of wirings is exposed from each of the plurality of openings,
wherein the part of each of the plurality of wirings exposed from each of the plurality of openings is an electrode terminal,
wherein the semiconductor chip is mounted over the first main surface of the first insulating layer of the wiring substrate such that the obverse surface thereof faces the first main surface and each of the plurality of electrode pads of the semiconductor chip is electrically connected to each of the plurality of electrode terminals of the wiring substrate via a metal bump,
wherein a plurality of first electrode terminals are arranged at a first region corresponding to a peripheral portion of the first main surface of the first insulating layer of the wiring substrate,
wherein a plurality of second electrode terminals are arranged at a second region located inside the first region and corresponding to a vicinity of a central portion of the first main surface of the first insulating layer of the wiring substrate,
wherein parts of the plurality of through-hole wiring portions electrically connected to parts of the plurality of wirings of which the plurality of the first electrode terminals are composed are disposed in a third region between the first and second regions, and
wherein, a number of the plurality of first electrode terminals is larger than a number of the plurality of second electrode terminals.
2. The semiconductor device according to claim 1 , wherein each of the plurality of through-hole wiring portions contains copper.
3. The semiconductor device according to claim 1 ,
wherein the plurality of first electrode terminals are arranged in two rows comprising an inside row and an outside row, and
wherein the first electrode terminals arranged in the inside row are electrically connected to the plurality of through-hole wiring portions disposed in the third region.
4. The semiconductor device according to claim 3 , wherein all of the first electrode terminals arranged in the outside row are first signal electrode terminals, and
wherein the first electrode terminals arranged in the inside row include a plurality of second signal electrode terminals, a plurality of first power supply electrode terminals, and a plurality of first ground (GND) electrode terminals.
5. The semiconductor device according to claim 4 , wherein the plurality of second electrode terminals include a plurality of second power supply electrode terminals and a plurality of second ground (GND) electrode terminals.
6. The semiconductor device according to claim 1 , wherein the plurality of first electrode terminals are arranged in a staggered pattern.
7. The semiconductor device according to claim 1 , wherein the plurality of second electrode terminals are arranged in a staggered pattern.
8. The semiconductor device according to claim 1 , wherein the wiring substrate is a coreless substrate without a core layer.
9. The semiconductor device according to claim 1 , wherein a shape of the metal bump is cylindrical shape.
10. The semiconductor device according to claim 1 , wherein a plurality of solder balls are disposed on the second main surface of the first insulating layer of the wiring substrate.