Semiconductor devices with a thermally conductive layer and methods of their fabrication
View Patent ↗An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.
1. A semiconductor device comprising:
a semiconductor substrate that includes a host substrate, an upper surface, and a channel;
an active area proximate the upper surface of the semiconductor substrate;
a substrate opening in the semiconductor substrate wherein a bottom of the substrate opening is defined by a recessed surface of the semiconductor substrate; and
a thermally conductive layer disposed over the semiconductor substrate and over the channel that contacts the recessed surface of the semiconductor substrate and extends between the recessed surface of the semiconductor substrate and a portion of the semiconductor substrate within the active area, the thermally conductive layer comprising a substantially electrically insulating layer within the active area.
2. The semiconductor device of claim 1 , further comprising an isolation region that includes the substrate opening.
3. The semiconductor device of claim 2 , wherein the thermally conductive layer comprises a substantially electrically insulating layer within the isolation region.
4. A semiconductor device comprising:
a semiconductor substrate that includes a host substrate, a channel, and an upper surface;
an active area proximate the upper surface of the semiconductor substrate;
a substrate opening in the semiconductor substrate wherein a bottom of the substrate opening is defined by a recessed surface of the semiconductor substrate;
a thermally conductive layer disposed over the semiconductor substrate that contacts the recessed surface of the semiconductor substrate and extends between the recessed surface of the semiconductor substrate and a portion of the semiconductor substrate within the active area, the thermally conductive layer comprising a substantially electrically insulating layer within the active area;
a gate electrode disposed over the upper surface of the semiconductor substrate and electrically coupled to the channel; and
a current-carrying electrode disposed over the upper surface of the semiconductor substrate and electrically coupled to the channel, wherein a heat generating region is present between the gate electrode and the current-carrying electrode, and the thermally conductive layer extends between the recessed surface of the semiconductor substrate and a portion of the semiconductor substrate over the heat generating region.
5. The semiconductor device of claim 4 , wherein a thermal path distance between the heat generating region and the substrate opening is less than 30 microns.
6. A semiconductor device comprising:
a semiconductor substrate that includes a host substrate, an upper surface, and a channel;
an active area proximate the upper surface of the semiconductor substrate;
a substrate opening in the semiconductor substrate wherein a bottom of the substrate opening is defined by a recessed surface of the semiconductor substrate; and
a thermally conductive layer disposed over the semiconductor substrate that contacts the recessed surface of the semiconductor substrate and extends between the recessed surface of the semiconductor substrate and a portion of the semiconductor substrate within the active area, the thermally conductive layer comprising a substantially electrically insulating layer within the active area; and
a first dielectric layer between the thermally conductive layer and a portion of the semiconductor substrate that includes the channel.
7. The semiconductor device of claim 6 , wherein the first dielectric layer further comprises one or more layers selected from silicon nitride, diamond, silicon carbide, boron nitride, aluminum nitride, graphite, poly diamond, or diamond-like materials.
8. The semiconductor device of claim 1 , wherein the thermally conductive layer comprises one or more material layers selected from diamond, silicon carbide, boron nitride, aluminum nitride, graphite, poly diamond, diamond-like materials, gold, silver, aluminum, or copper.
9. The semiconductor device of claim 1 , wherein the thermally conductive layer has a thermal conductivity greater than 200 watts per meter-Kelvin.
10. The semiconductor device of claim 1 , wherein the recessed surface is substantially co-planar with an upper surface of the host substrate.
11. The semiconductor device of claim 1 , wherein the recessed surface is below an upper surface of the host substrate.
12. A semiconductor device comprising:
a semiconductor substrate that includes a host substrate and an upper surface;
an active area proximate the upper surface of the semiconductor substrate;
a substrate opening in the semiconductor substrate wherein a bottom of the substrate opening is defined by a recessed surface of the semiconductor substrate;
a thermally conductive layer disposed over the semiconductor substrate that contacts the recessed surface of the semiconductor substrate and extends between the recessed surface of the semiconductor substrate and a portion of the semiconductor substrate within the active area, the thermally conductive layer comprising a substantially electrically insulating layer within the active area; and
a through wafer via formed between the substrate opening and a lower surface of the semiconductor substrate.
13. The semiconductor device of claim 12 , wherein the through wafer via is lined with a back-metal layer.
14. The semiconductor device of claim 13 , wherein the back-metal layer contacts the thermally conductive layer.
15. The semiconductor device of claim 1 , wherein the thermal boundary resistance between the thermally conductive layer and the recessed surface is less than 30 square meters-Kelvin per gigawatt.
16. A transistor comprising:
a semiconductor substrate that includes a host substrate, an upper surface, and a channel comprising one or more group III-N semiconductor layers;
an active area that includes the channel;
a gate electrode disposed over the upper surface of the semiconductor substrate in the active area and electrically coupled to the channel;
a source electrode and a drain electrode disposed over the upper surface of the semiconductor substrate in the active area on opposite sides of the gate electrode and electrically coupled to the channel, wherein a heat generating region is present between the gate electrode and the drain electrode;
a substrate opening in the semiconductor substrate wherein a bottom of the substrate opening is defined by a recessed surface of the semiconductor substrate; and
a thermally conductive layer disposed over the semiconductor substrate and over the heat generating region that contacts the recessed surface of the semiconductor substrate and extends between the recessed surface of the semiconductor substrate and a portion of the semiconductor substrate within the active area, the thermally conductive layer comprising a substantially electrically insulating layer within the active area.
17. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate that includes a channel;
creating an isolation region that defines an active area along an upper surface of the semiconductor substrate;
forming a gate electrode over the semiconductor substrate over the channel in the active area;
forming a source electrode and a drain electrode disposed over the upper surface of the semiconductor substrate in the active area on opposite sides of the gate electrode and electrically coupled to the channel;
forming a substrate opening in the semiconductor substrate, wherein a bottom of the substrate opening is defined by a recessed surface of the semiconductor substrate; and
depositing a thermally conductive layer over the semiconductor substrate that contacts the recessed surface of the semiconductor substrate and extends between the recessed surface of the semiconductor substrate and a portion of the semiconductor substrate over the channel, the thermally conductive layer comprising a substantially electrically insulating layer within the active area.
18. The method of claim 17 , further comprising depositing a first dielectric layer over and in contact with the semiconductor substrate.
19. The method of claim 17 , wherein the semiconductor substrate includes a host substrate, and the method further comprises forming the substrate opening so that the recessed surface is below an upper surface of the host substrate.
20. The method of claim 18 , wherein the semiconductor substrate includes a host substrate, and the method further comprises forming the substrate opening so that the recessed surface is above an upper surface of the host substrate.