Patent Assignment
Reel/Frame 033462/0267
Supplement to Ip Security Agreement
Recorded: 2014-08-01
Pages: 19
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2014-07-29
Assignee
CITIBANK, N.A., AS NOTES COLLATERAL AGENT
390 GREENWICH STREET, NEW YORK, NEW YORK, 10013
Covered Properties
(207)
System and Method for Conditional Task Switching During Ordering Scope Transitions
System and Method for Conditional Task Switching During Ordering Scope Transitions
Integrated Circuit Electrical Protection Device
Test Mode Entry Interlock
Solder Pad for Semiconductor Device Package
Implant for Performance Enhancement of Selected Transistors in an Integrated Circuit
Real-Time Distributed Network Slave Device, Real-Time Distributed Network and Method Therefor
Multi-Level Clock Signal Distribution Network and Integrated Circuit
Integrated Circuit with Lbist Sub-Partitions
Application:
14/246,131 →
Publication:
US US20150285859A1
Tamper Detector Power Supply with Wake-Up
Memory Access Scheme for System on Chip
Collapsible Probe Tower Device and Method of Forming Thereof
Routing Standard Cell-Based Integrated Circuits
Interrupt Controller and a Method of Controlling Processing of Interrupt Requests by a Plurality of Processing Units
Semiconductor Wafer and Method of Concurrently Testing Circuits Formed Thereon
Defective Die Replacement in a Die Stack
Method and Apparatus for Providing Memory Protection
Cavity-Down Pressure Sensor Device
Clock Distribution Architecture for Integrated Circuit
Storage and Retrieval of Information Using Internet Protocol Addresses
Application:
14/248,354 →
Publication:
US US20150295883A1
Hardware Accelerator for Tunnel Processing
Application:
14/248,363 →
Publication:
US US20150295729A1
Semiconductor Devices with a Thermally Conductive Layer and Methods of Their Fabrication
Content Addressable Memory with Error Detection
Method and Apparatus for Monitoring General Purpose Input Output, Gpio, Signals
Debug Configuration Tool with Layered Graphical User Interface
Method of Dtx Detection in a Wireless Communication System
Method of Discontinuous Transmission Detection
Ratioless Near-Threshold Level Translator
Synchronization and Frequency Correction for a Receiver
Patent:
9,137,083 →
Application:
14/255,265 →
Systems and Methods for Multiple Ball Bond Structures
Application:
14/255,450 →
Publication:
US US20150303169A1
Multi-Use Substrate for Integrated Circuit
Systems and Methods for Managing Branch Target Buffers in a Multi-Threaded Data Processing System
Application:
14/256,020 →
Publication:
US US20150301829A1
Circuit and Method for Speed Monitoring of an Electric Motor
Clock Signal Generator Module, Integrated Circuit, Electronic Device and Method Therefor
Sensor Package Having Stacked Die
Semiconductor Sensor with Gel Filled Cavity
Multi-Core Processor for Managing Data Packets in Communication Network
Apparatus for Error Detection in Memory Devices
Device and Method for Synchronization in a Mobile Communication System
Patent:
9,094,908 →
Application:
14/258,394 →
Synchronization Circuitry, Common Public Radio Interface Enable Device, and a Method of Synchronizing a Synchronized Clock Signal of a Second Transceiver to a Clock of a First Transceiver
Temperature Sensor Circuitry with Scaled Voltage Signal
Memory with Redundancy
Method for Improving E-Beam Lithography Gate Metal Profile for Enhanced Field Control
Adaptive Control of an Audio Unit Using Motion Sensing
Application:
14/259,971 →
Publication:
US US20150309767A1
Semiconductor Device and Related Fabrication Methods
Semiconductor Packages Having Wire Bond Wall to Reduce Coupling
Method and Apparatus for Booting Processor
Microprocessor, and Method of Managing Reset Events Therefor
Microprocessor Device, and Method of Managing Reset Events Therefor
Direct Sequence Spread Spectrum Signal Receiving Device and Method
Method and Apparatus for Deriving a Packet Select Probability Value
System Performance Control Component and Method Therefor
Charge Pump Ldo with Secondary Sensing for Low Power Need Based Refresh
Semiconductor Package and System with an Isolation Structure to Reduce Electromagnetic Coupling
Imminent Read Failure Detection Using High/Low Read Voltage Levels
Imminent Read Failure Detection Based Upon Unacceptable Wear For NVM Cells
Imminent Read Failure Detection Based Upon Changes In Error Voltage Windows For NVM Cells
Structures for Reducing Corrosion in Wire Bonds
Bond Pad and Passivation Layer Having a Gap and Method for Forming
Patent:
9,111,755 →
Application:
14/262,417 →
Power Safety Circuit, Integrated Circuit Device and Safety Critical System
Reference Voltage Generating Circuit, Integrated Circuit and Voltage or Current Sensing Device
Application:
14/354,284 →
Publication:
US US20140285175A1
Method of Controlling a Thermal Budget of an Integrated Circuit Device, an Integrated Circuit, a Thermal Control Module and an Electronic Device Therefor
Application:
14/354,286 →
Publication:
US US20140303804A1
Scan Flip-Flop
Patent:
9,081,061 →
Application:
14/262,789 →
Testing Operation of Multi-Threaded Processor Having Shared Resources
Application:
14/262,793 →
Publication:
US US20150309847A1
Spare Gate Cell for Integrated Circuit
Heat Sink Having a Through-Opening
Identification Mechanism for Semiconductor Device Die
Application:
14/263,460 →
Publication:
US US20140232017A1
Lead Frames Having Metal Traces with Metal Stubs
Application:
14/264,071 →
Publication:
US US20150311143A1
Semiconductor Device Having a Test Controller and Method of Operation
Differential Pair Sensing Circuit Structures
CONFIGURABLE PERIPHERAL COMPONENENT INTERCONNECT EXPRESS (PCIe) CONTROLLER
Configurable Power Amplifier and Related Construction Method
Non-Volatile Memory Using Bi-Directional Resistive Elements
Systems and Methods for Data Conversion
Error Correction with Secondary Memory
Segmented Driver for a Transistor Device
Power Amplifier with Envelope Injection
Techniques for Electromigration Stress Mitigation in Interconnects of an Integrated Circuit Design
Aluminum Clad Copper Structure of an Electronic Component Package and a Method of Making an Electronic Component Package with an Aluminum Clad Copper Structure
Dual-Edge Gated Clock Signal Generator
Encapsulant for a Semiconductor Device
Patent:
9,093,383 →
Application:
14/268,420 →
Apparatus and Method for Preventing Multiple Resets
Method of Fabricating a Tunable Schottky Diode with Depleted Conduction Path
Three-Dimensional Solar Cell Having Increased Efficiency
Application:
14/270,986 →
Publication:
US US20140238483A1
Pre-Formed via Array for Integrated Circuit Package
Patent:
9,064,718 →
Application:
14/271,469 →
Composite Semiconductor Device with Multiple Threshold Voltages
Power Supply Slew Rate Detector
Secure Boot on Deep Sleep Wake-Up
Patent:
9,158,921 →
Application:
14/274,770 →
Power Mosfet Structure and Method
Programmable Stitch Chaining of Die-Level Interconnects for Reliability Testing
Reconfigurable Circuit and Decoder Therefor
Non-Leaded Type Semiconductor Package and Method of Assembling Same
Wafer Level Pacakges Having Non-Wettable Solder Collars and Methods for the Fabrication Thereof
Data Processing System and Method of Controlling Access to a Shared Memory Unit
Memory Access Controller, Data Processing System, and Method for Managing Data Flow Between a Memory Unit and a Processing Unit
Application:
14/358,051 →
Publication:
US US20140300615A1
Integrated Circuit Device, Asymmetric Multi-Core Processing Module, Electronic Device and Method of Managing Execution of Computer Program Code Therefor
Application:
14/358,053 →
Publication:
US US20140325183A1
Semiconductor Package with Stress Relief and Heat Spreader
Waveform Conversion Circuit with Reduced Jitter
State Retention Power Gated Cell
System for Monitoring and Controlling the Power of a Radio Frequency (Rf) Signal in a Short-Range Rf Transmitter
Semiconductor Device with Composite Drift Region and Related Fabrication Method
Timing Verification of an Integrated Circuit
Method for Placing Operational Cells in a Semiconductor Device
Method, Device and Computer Program Product for Measuring User Perception Quality of a Processing System Comprising a User Interface
Application:
14/358,740 →
Publication:
US US20150286551A1
Self-Bootstrap Driving Circuit and Dc-Dc Converter
Error Pad for Safety Device
Single Power Supply Level Shifter
Supply-Switching System
Scan Flip-Flop Circuit with Los Scan Enable Signal
Housing for Electronic Devices
Application:
14/281,917 →
Publication:
US US20150342069A1
Stacked Die Package with Redistribution Layer
Application:
14/281,918 →
Publication:
US US20150340305A1
Capacitance-To-Voltage Interface Circuits
System and Method for Selectively Allocating Entries at a Branch Target Buffer
Supply Voltage Regulation with Temperature Scaling
Processing System and Method of Operating a Processing System
Application:
14/283,320 →
Publication:
US US20150339178A1
Adaptive Scheduling Queue Control for Memory Controllers Based Upon Page Hit Distance Determinations
Processing Device and Method of Executing an Instruction Sequence
Processing Device and Method for Performing a Stage of a Fast Fourier Transform
Integrated Circuit, Integrated Circuit Package and Method of Providing Protection Against an Electrostatic Discharge Event
System-On-Chip, Method of Manufacture Thereof and Method of Controlling a System-On-Chip
Application:
14/359,709 →
Publication:
US US20150178102A1
Semiconductor Device with Vias on a Bridge Connecting Two Buses
Lead-Frame Circuit Package
Application:
14/285,079 →
Publication:
US US20140252570A1
Controller, Sata System and Method of Operation Therefor
Phase Shift and Attenuation Circuits for Use with Multiple-Path Amplifiers
Semiconductor Devices That Include a Die Bonded to a Substrate with a Gold Interface Layer
Methods for Bonding a Die and a Substrate
Laterally Diffused Metal Oxide Semiconductor Transistors for Radio Frequency Power Amplifiers
Systems and Methods for a Low Dropout Voltage Regulator
Non-Volatile Memory Using Bi-Directional Resistive Elements
Converter Unit for an M-Order Digital Modulation and a Method Thereof
Inductive Element with Interrupter Region and Method for Forming
System for Testing Integrated Circuit
Apparatus for Measuring Signal Skew of Asynchronous Flash Memory Controller
Timing Event Generation Circuit for Wireless Communication Apparatus
Input/Output Cell, Integrated Circuit Device and Methods of Providing on-Chip Test Functionality
Non-Volatile Memory Using Bi-Directional Resistive Elements
Processor Unit for Determining a Quality Indicator of a Communication Channel and a Method Thereof
Patent:
9,100,115 →
Application:
14/288,525 →
Apparatus for and a Method of Making a Hierarchical Integrated Circuit Design of an Integrated Circuit Design, a Computer Program Product and a Non-Transitory Tangible Computer Readable Storage Medium
Explicit Barrier Scheduling Mechanism for Pipelining of Stream Processing Algorithms
Split Gate Memory Cell with a Layer of Nanocrystals with Improved Erase Performance
Electrostatic Discharge Protection System
Semiconductor Wafer and Method of Concurrently Testing Circuits Formed Thereon
Active Tiling Placement for Improved Latch-up Immunity
Application:
14/289,730 →
Publication:
US US20140264728A1
Sensor Package Including a Magnetic Field Sensor and a Continuous Coil Structure for Enabling Z-Axis Self-Test Capability
Mems Device Having Variable Gap Width and Method of Manufacture
Indicating Internal Transmitter Errors in a Controller Area Network (Can)
Method of Making a Split Gate Non-Volatile Memory (Nvm) Cell and a Logic Transistor
Method of Making a Split Gate Non-Volatile Memory (Nvm) Cell
Multiplying Digital to Analog Converter (Mdac) with Error Compensation and Method of Operation
Patent:
9,112,523 →
Application:
14/291,355 →
Split Gate Nanocrystal Memory Integration
Microelectronic Packages Having Sidewall-Deposited Heat Spreader Structures and Methods for the Fabrication Thereof
Apparatus and Method for Placing Stressors on Interconnects Within an Integrated Circuit Device to Manage Electromigration Failures
Stiffened Semiconductor Die Package
Resonating Filter and Method Thereof
Correlation of Test Results and Test Coverage for an Electronic Device Design
Device and Method for Connecting an Rf Generator to a Coaxial Conductor
Electronic Systems and Methods for Integrated, Automatic, Medium-Quality Audio
Using Distributed Network Elements to Send Authoritative DNS Responses
Application:
14/294,298 →
Publication:
US US20150350154A1
Integrated Electronic Package and Method of Fabrication
Methods and Structures for Charge Storage Isolation in Split-Gate Memory Arrays
Patent:
9,136,360 →
Application:
14/297,657 →
Driver Amplifier Systems and Methods of Their Operation
System and Method for Conditional Task Switching During Ordering Scope Transitions
Field Focusing Features in a Reram Cell
Ldmos Minority Carrier Shunting
Semiconductor Device Having Power Distribution Using Bond Wires
Data Processing Unit and Method for Operating a Data Processing Unit
Application:
14/302,509 →
Publication:
US US20150363227A1
Margin Tool for Double Data Rate Memory Systems
Methods And Systems For Gate Dimension Control In Multi-Gate Structures For Semiconductor Devices
3D Device Packaging Using Through-Substrate Posts
Methods and Structures for Split Gate Memory Cell Scaling with Merged Control Gates
Radio Frequency Coupling Structure
Integrated Circuit Package with Radio Frequency Coupling Arrangement
Integrated Circuit Package with Radio Frequency Coupling Structure
Tin-Based Wirebond Structures
Application:
14/305,277 →
Publication:
US US20140367859A1
Wireless Communication System with Sipto Continuity
Insulated Wire Bonding with Efo Before Second Bond
Patent:
9,165,904 →
Application:
14/306,254 →
Method of, and a Device for Updating a Multiple-Processing Entity Packet Management System, and Associated Computer Program Product
Techiques for Time-Domain Frame Synchronization of Packets
Method of Trimming Current Source Using on-Chip Adc
Power Device Termination Structures and Methods
Method and Apparatus for Handling Incoming Data Frames
Etch Release Residue Removal Using Anhydrous Solution
Shallow Trench Isolation for Soi Structures Combining Sidewall Spacer and Bottom Liner
Application:
14/308,816 →
Publication:
US US20140299935A1
Processing Device and Method of Compressing Images
Latching Level Shifter and Method of Operation
Patent:
9,191,007 →
Application:
14/310,579 →
Control Gate Driver for Use with Split Gate Memory Cells
System-In-Packages Having Vertically-Interconnected Leaded Components and Methods for the Fabrication Thereof
Methods of Producing Bipolar Transistors Having Emitter-Base Junctions of Varying Depths and/or Doping Concentrations
System and Method for Testing Address-Swap Faults in Multiport Memories
Devices with Signal Characteristic Dependent Control Circuitry and Methods of Operation Therefor
Surface Finish for Wirebonding
Integrated Circuit Package with Voltage Distributor
Flip-Flop Having Shared Feedback and Method of Operation
Radio Frequency Devices with Surface-Mountable Capacitors for Decoupling and Methods Thereof
Microelectronic Packages Having Embedded Sidewall Substrates and Methods for the Producing Thereof
System on a Chip with Managing Processor and Method Therefor
System on a Chip, Controller and Method for Securing Data
Application:
14/316,884 →
Publication:
US US20150379276A1
MEMS Fabrication Process with Two Cavities Operating at Different Pressures
Integrated Passive Device Assemblies for Rf Amplifiers, and Methods of Manufacture Thereof
Method and Apparatus for a Multi-Harmonic Matching Network
Adaptive High-Order Nonlinear Function Approximation Using Time-Domain Volterra Series to Provide Flexible High Performance Digital Pre-Distortion
Monolithic Transistor Circuits with Tapered Feedback Resistors, Rf Amplifier Devices, and Methods of Manufacture Thereof
Methods for Bonding Semiconductor Wafers
Microelectromechanical Systems Devices with Improved Lateral Sensitivity
Memory Controller
Integrated Circuit with Internal and External Voltage Regulators
Integrated Circuit Design Synthesis Using Slack Diagrams
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 1, 2014
From: XU, ZHENG; JOKINEN, TOMMI M.; MOYER, WILLIAM C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032569/0158 →
Assignment of Assignor's Interest
Apr 1, 2014
From: XU, ZHENG; JOKINEN, TOMMI M.; MOYER, WILLIAM C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032569/0087 →
Assignment of Assignor's Interest
Apr 1, 2014
From: STOCKINGER, MICHAEL A.; ZHANG, WENZHONG; ZHANG, XU
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032570/0388 →
Assignment of Assignor's Interest
Apr 2, 2014
From: EDWARDS, WILLIAM E.; HALL, JOHN M.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032584/0265 →
Assignment of Assignor's Interest
Apr 2, 2014
From: SARIHAN, VIJAY; GONG, ZHIWEI; HAYES, SCOTT M.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032586/0426 →
Assignment of Assignor's Interest
Apr 4, 2014
From: MOHEBAN, LIOR; ELAZARY, AVI; NAVE, AMIR; SIVAN, NOAM
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 032600/0644 →
Assignment of Assignor's Interest
Apr 4, 2014
From: EDMISTON, GRAHAM
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 032600/0349 →
Assignment of Assignor's Interest
Apr 7, 2014
From: UEHLING, TRENT S.; FOLTS, KELLY F.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032615/0301 →
Assignment of Assignor's Interest
Apr 7, 2014
From: PRAKASH, SIDDI JAI; ABHISHEK, KUMAR; BHARGAVA, PRASHANT; STOCKINGER, MICHAEL A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032621/0336 →
Assignment of Assignor's Interest
Apr 7, 2014
From: JAJODIA, REECHA; ANAND, GAGAN; JINDAL, ANURAG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032621/0330 →
Assignment of Assignor's Interest
Apr 7, 2014
From: MCMENAMIN, DAVID; SCOBIE, JAMES ANDREW COLLIER
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032619/0598 →
Assignment of Assignor's Interest
Apr 7, 2014
From: MACDONALD, COLIN; JARRAR, ANIS M.; MASON, KRISTEN L.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032617/0423 →
Assignment of Assignor's Interest
Apr 8, 2014
From: PELLEY, PERRY H.; MCSHANE, MICHAEL B.; PHAM, TIM V.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032628/0601 →
Assignment of Assignor's Interest
Apr 8, 2014
From: HUMPHRIES, GERARD WILLIAM; ROBERTSON, ALISTAIR PAUL
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032628/0942 →
Assignment of Assignor's Interest
Apr 8, 2014
From: KILLINGSWORTH, DEWEY
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032621/0606 →
Assignment of Assignor's Interest
Apr 9, 2014
From: SINGH, NITIN; JAIN, GAURAV; JINDAL, AMIT; TOMAR, ROHIT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032631/0063 →
Supplement to Ip Security Agreement
Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
Supplement to Ip Security Agreement
Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
Assignment and Assumption of Security Interest in Patents
Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
Assignment and Assumption of Security Interest in Patents
Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
Security Agreement Supplement
Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
Supplement to the Security Agreement
Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
Corrective Assignment to Correct the Remove Application 12092129 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
Corrective Assignment of Incorrect Application 14/258,829 Previously Recorded on Reel 037444 Frame 0109. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →