IP Library Granted Patent US 9,281,375
Granted Patent B2
US 9,281,375 · App. 14/313,114 · Granted Mar 8, 2016

Methods of producing bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations

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Quick Facts
Patent No.
US 9,281,375
App. No.
14/313,114
Granted
Mar 8, 2016
Kind
B2
Abstract

Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

Claims (40)

1. A method for producing a bipolar transistor, comprising:

providing a semiconductor-containing substrate with an upper surface, and having therein a buried layer collector region of a first conductivity type located below the upper surface and of a buried layer collector region doping concentration, wherein a first portion of the substrate located below the buried layer collector region and a second portion of the substrate located above the buried layer collector region are of a second, opposite conductivity type;

during one or more first doping steps, forming in the second portion of the substrate first and second adjacent emitter regions of the first conductivity type near the first surface, the first emitter region extending substantially to the first surface and laterally separated from the buried layer collector region; and

during one or more second doping steps, forming in the second portion of the substrate first and second adjacent base regions of the second conductivity type, respectively, beneath the first and second emitter regions, wherein the first base region has a first base region doping concentration and the second base region has a second base region doping concentration different than the first base region doping concentration, and the first emitter region and first base region providing a first NP or PN junction at a first depth beneath the upper surface, and the second emitter region and the second base region providing a second NP or PN junction at a second depth beneath the upper surface.

2. The method of claim 1 , further comprising providing at least one isolation region substantially at the upper surface, wherein the second emitter region and the second base region substantially underlie the at least one isolation region.

3. The method of claim 1 , wherein the one or more first doping steps and the one or more second doping steps are performed during one or more chain implants of dopants of opposite conductivity type.

4. The method of claim 1 , wherein the buried layer collector region and the second base region are laterally arranged so that the buried layer collector region extends underneath the second base region.

5. The method of claim 1 , wherein the buried layer collector region and the second base region are laterally arranged so that the buried layer collector region does not extend underneath the second base region.

6. The method of claim 1 , further comprising forming a third emitter region and third base region having an NP or PN junction there between, laterally arranged on a side of the first emitter region opposite the second emitter region.

7. A method for producing a bipolar transistor, comprising:

forming first emitter region of a first conductivity type in a semiconductor substrate having a first emitter region doping concentration;

forming a first base region of a second, opposite conductivity type in the semiconductor substrate underlying the first emitter region and having a first base region doping concentration, the first base region forming a first PN or NP junction with the first emitter region at a first depth from a first surface of the semiconductor substrate;

forming a second emitter region of the first conductivity type in the semiconductor substrate having a second emitter region doping concentration and Ohmically coupled to the first emitter region;

forming a second base region of the second conductivity type in the semiconductor substrate underlying the second emitter region and having a second base region doping concentration greater than the first base doping concentration, the second base region forming a second PN or NP junction with the second emitter region at a second depth from the first surface less than the first depth; and

forming a buried layer collector region of the first conductivity type in the substrate underlying the first surface and laterally spaced a third distance from the first emitter region.

8. The method of claim 7 , wherein the first emitter region and the second emitter region are formed at laterally adjacent locations.

9. The method of claim 7 , wherein the first base region and the second base region are formed at laterally adjacent locations.

10. The method of claim 7 , wherein the second emitter region is formed to extend laterally at least partly between the first emitter region and the buried layer collector region.

11. The method of claim 7 , wherein the second base region is formed to extend laterally at least partly between the first base region and the buried layer collector region.

12. The method of claim 7 , further comprising:

forming a third emitter region of a third emitter doping concentration coupled to the first emitter region; and

forming a third base region of a third base doping concentration coupled to the first base region, the third base doping concentration is less than the first base doping concentration.

13. The method of claim 7 , wherein the second emitter region is formed to have a lateral extent greater than the third distance.

14. The method of claim 7 , wherein the second emitter region is formed to have a lateral extent less than the third distance.

15. A method for producing a bipolar transistor, comprising:

forming a first emitter region of a first conductivity type in a semiconductor substrate having a first emitter region doping concentration;

forming a first base region of a second, opposite conductivity type in the semiconductor substrate underlying the first emitter region and having a first base region doping concentration, the first base region forming a first PN or NP junction with the first emitter region at a first depth from a first surface of the semiconductor substrate;

forming a second emitter region of the first conductivity type in the semiconductor substrate having a second emitter region doping concentration and Ohmically coupled to the first emitter region;

forming a second base region of the second conductivity type in the semiconductor substrate underlying the second emitter region and having a second base region doping concentration, the second base region forming a second PN or NP junction with the second emitter region at a second depth from the first surface, the second depth shallower than the first depth;

forming an isolation feature overlying the second emitter region; and

forming an emitter contact in the first emitter region and adjacent the isolation feature, the juncture between the emitter contact and the isolation feature generally aligning with the juncture between the first emitter region and the second emitter region and the juncture between the first base region and the second base region.

16. The method of claim 15 wherein the second base doping concentration is greater than the first base doping concentration.

17. The method of claim 15 , wherein the first emitter region and the second emitter region are formed in an upper epitaxial layer of the semiconductor substrate.

18. The method of claim 17 , wherein the buried layer collector region is formed, at least in substantial part, in a lower epitaxial layer of the semiconductor substrate.

19. The method of claim 15 , further comprising:

forming a base contact over the semiconductor substrate;

forming a WELL region of the second conductivity type in ohmic contact with the base contact; and

forming a buried layer collector region of the first conductivity type in the semiconductor substrate underlying the first surface and having a portion extending under the WELL region;

wherein the second emitter region is formed to extend laterally from the first emitter region to the WELL region.

20. The method of claim 15 , wherein the second emitter region is formed to have a doping concentration less than the first emitter region doping concentration by a factor of about 1 to 100, and wherein the second base region is formed to have a doping concentration greater than the first base region doping concentration by a factor of about 1 to 10.

Assignments (16)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
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From: FREESCALE SEMICONDUCTOR, INC.
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