Timing verification of an integrated circuit
View Patent ↗This disclosure describes a design tool that verifies timing of an integrated circuit design by partitioning the integrated circuit design's gate-level netlist into target cell partition netlists and performs transistor-level circuit simulation on each target cell partition netlist. The design tool performs a back tracing procedure on each target sequential cell to define the target cell partition netlists. The design tool then identifies timing modes that enable valid logical paths through the target cell partition netlists from source sequential cells to the target sequential cells. In turn, the design tool performs transistor-level circuit simulation (e.g., SPICE simulations) on each target cell partition netlist to check for timing violations based upon the timing modes. In one embodiment, the design tool includes clock tree delay information, power supply variations, or routing parasitic information in the simulations to achieve improved timing analysis accuracy compared with traditional static timing analysis or timing optimization.
1. A method for optimizing timing of an integrated circuit design, the method comprising:
partitioning an integrated circuit gate-level netlist into a plurality of target cell partition netlists, wherein each of the plurality of target cell partition netlists comprises one or more target sequential cells and one or more source sequential cells;
performing one or more transistor-level circuit simulations on each of the plurality of target cell partition netlists, the one or more transistor-level circuit simulations resulting in a plurality of timing simulation results; and
generating mask layer data in response to a determination that the plurality of timing simulation results do not generate one or more timing violations, wherein the mask layer data is configured to generate a plurality of masks for construction of an integrated circuit corresponding to the integrated circuit gate-level netlist.
2. The method of claim 1 further comprising:
matching a plurality of routing parasitic properties to a plurality of local nodes included in the plurality of target cell partition netlists, wherein the plurality of routing parasitic properties were generated in response to a place and route stage of the integrated circuit design; and
inserting the matched plurality of routing parasitic properties into the plurality of target cell partition netlists, wherein the transistor-level circuit simulation utilizes the routing parasitic properties during the transistor-level circuit simulations.
3. The method of claim 2 wherein the plurality of local nodes correspond to wire interconnections between standard cell instances, and wherein at least one of the plurality of routing parasitic properties are selected from the group consisting of wire loading capacitances, wire loading resistances, and fan out loading.
4. The method of claim 1 wherein the partitioning further comprises:
selecting one of the one or more target sequential cells;
back tracing, from the selected target sequential cell, through combinational logic included in the integrated circuit gate-level netlist until reaching the one or more source sequential cells; and
defining one of the plurality of target cell partition netlists as comprising the selected target sequential cell, the one or more source sequential cells, and the back traced combinational logic.
5. The method of claim 1 further comprising:
defining a clock tree partition, from a clock tree corresponding to the integrated circuit gate-level netlist, wherein the clock tree partition comprises a target sequential cell clock node corresponding to the target sequential cell and a source sequential cell clock node corresponding to a selected one of the one or more source sequential cells;
determining a clock skew between the selected source sequential cell clock node and the target sequential cell clock node; and
inserting the clock skew into the selected target cell partition netlist, wherein the transistor-level circuit simulation utilizes the clock skew during the transistor-level circuit simulation of the selected target cell partition netlist.
6. The method of claim 1 wherein a selected target cell partition netlist comprises a plurality of standard cell instances, the method further comprising:
matching a plurality of voltage supply values to the plurality of standard cell instances, wherein the plurality of voltage supply values are based upon a power grid simulation corresponding to the integrated circuit design; and
inserting the plurality of voltage supply values into the selected target cell partition netlist at the matched plurality of standard cell instances, wherein the transistor-level circuit simulation utilizes the plurality of voltage supply values during the transistor-level circuit simulation of the selected target cell partition netlist.
7. The method of claim 1 further comprising:
selecting one of the plurality of target cell partition netlists;
detecting a plurality of source sequential cells in the selected target cell partition netlist, the one or more source sequential cells included in the plurality of source sequential cells;
performing gate-level simulation on the selected target cell partition netlist by injecting input stimulus to each of the plurality of source sequential cells, wherein the gate-level simulation generates one or more input toggle events;
determining one or more timing modes of the target cell partition netlist based upon the generated one or more input toggle events; and
utilizing the one or more timing modes during the transistor-level circuit simulation of the selected target cell partition netlist.
8. The method of claim 1 wherein each of the plurality of target cell partition netlists are individually executed by one of a plurality of SPICE simulators.
9. The method of claim 1 wherein:
the integrated circuit design utilizes a plurality of standard cells; and
the transistor-level circuit simulation is devoid of using one or more liberty files corresponding to the plurality of standard cells.
10. The method of claim 9 wherein the integrated circuit executes under one or more timing margins that are less than one or more corresponding timing margins required by the one or more liberty files.
11. A system comprising:
one or more processors;
a memory accessible by the one or more processors;
a design tool system executed by at least one of the one or more processors and configured to:
partition an integrated circuit gate-level netlist into a plurality of target cell partition netlists, wherein each of the plurality of target cell partition netlists comprises one or more target sequential cells and one or more source sequential cells;
perform one or more transistor-level circuit simulations on each of the plurality of target cell partition netlists, the one or more transistor-level circuit simulations resulting in a plurality of timing simulation results; and
generate mask layer data in response to a determination that the plurality of timing simulation results do not generate one or more timing violations, wherein the mask layer data is configured to generate a plurality of masks for construction of an integrated circuit corresponding to the integrated circuit gate-level netlist.
12. The system of claim 11 wherein the design tool system is further configured to:
match a plurality of routing parasitic properties to a plurality of local nodes included in the plurality of target cell partition netlists, wherein the plurality of routing parasitic properties were generated in response to a place and route stage of the integrated circuit design; and
insert the matched plurality of routing parasitic properties into the plurality of target cell partition netlists, wherein the transistor-level circuit simulation utilizes the routing parasitic properties during the transistor-level circuit simulations.
13. The system of claim 12 wherein the plurality of local nodes correspond to wire interconnections between standard cell instances, and wherein at least one of the plurality of routing parasitic properties are selected from the group consisting of wire loading capacitances, wire loading resistances, and fan out loading.
14. The system of claim 11 wherein the design tool system is further configured to:
select one of the one or more target sequential cells;
back trace, from the selected target sequential cell, through combinational logic included in the integrated circuit gate-level netlist until reaching the one or more source sequential cells; and
define one of the plurality of target cell partition netlists as comprising the selected target sequential cell, the one or more source sequential cells, and the back traced combinational logic.
15. The system of claim 11 wherein the design tool system is further configured to:
define a clock tree partition, from a clock tree corresponding to the integrated circuit gate-level netlist, wherein the clock tree partition comprises a target sequential cell clock node corresponding to the target sequential cell and a source sequential cell clock node corresponding to a selected one of the one or more source sequential cells;
determine a clock skew between the selected source sequential cell clock node and the target sequential cell clock node; and
insert the clock skew into the selected target cell partition netlist, wherein the transistor-level circuit simulation utilizes the clock skew during the transistor-level circuit simulation of the selected target cell partition netlist.
16. The system of claim 11 wherein a selected target cell partition netlist comprises a plurality of standard cell instances, and wherein the design tool system is further configured to:
match a plurality of voltage supply values to the plurality of standard cell instances, wherein the plurality of voltage supply values are based upon a power grid simulation corresponding to the integrated circuit design; and
insert the plurality of voltage supply values into the selected target cell partition netlist at the matched plurality of standard cell instances, wherein the transistor-level circuit simulation utilizes the plurality of voltage supply values during the transistor-level circuit simulation of the selected target cell partition netlist.
17. The system of claim 11 wherein the design tool system is further configured to:
select one of the plurality of target cell partition netlists;
detect a plurality of source sequential cells in the selected target cell partition netlist, the one or more source sequential cells included in the plurality of source sequential cells;
perform gate-level simulation on the selected target cell partition netlist by injecting input stimulus to each of the plurality of source sequential cells, wherein the gate-level simulation generates one or more input toggle events;
determine one or more timing modes of the target cell partition netlist based upon the generated one or more input toggle events; and
utilize the one or more timing modes during the transistor-level circuit simulation of the selected target cell partition netlist.
18. The system of claim 11 wherein each of the plurality of target cell partition netlists are individually executed by one of a plurality of SPICE simulators.
19. The system of claim 11 wherein:
the integrated circuit design utilizes a plurality of standard cells;
the transistor-level circuit simulation is devoid of using one or more liberty files corresponding to the plurality of standard cells; and
the integrated circuit executes under one or more timing margins that are less than one or more corresponding timing margins required by the one or more liberty files.
20. A computer program product stored in a computer readable storage medium, comprising computer program code that, when executed by an information handling system, causes the information handling system to perform actions comprising:
partitioning an integrated circuit gate-level netlist into a plurality of target cell partition netlists, wherein each of the plurality of target cell partition netlists comprises one or more target sequential cells and one or more source sequential cells;
performing one or more transistor-level circuit simulations on each of the plurality of target cell partition netlists, the one or more transistor-level circuit simulations resulting in a plurality of timing simulation results; and
generating mask layer data in response to a determination that the plurality of timing simulation results do not generate one or more timing violations, wherein the mask layer data is configured to generate a plurality of masks for construction of an integrated circuit corresponding to the integrated circuit gate-level netlist.