Semiconductor device with vias on a bridge connecting two buses
View Patent ↗A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.
1. A method for determining placement of vias in a semiconductor device comprising:
for a conductive bridge in the semiconductor device:
determining a width of a first conductive bus;
determining a width of a second conductive bus;
determining a width of the conductive bridge, wherein the conductive bridge is coupled between the first and second conductive buses; and
when the width of the conductive bridge is less than the width of the first conductive bus and the width of the second conductive bus, forming three conductive vias in the conductive bridge,
wherein a middle via of the three conductive vias is positioned a first distance along the conductive bridge from the first conductive bus that is greater than a first vacancy migration critical distance, and wherein the middle via of the three conductive vias is positioned a second distance along the conductive bridge from the second conductive bus that is greater than a second vacancy migration critical distance.
2. The method of claim 1 further comprising:
determining whether a volume of the first conductive bus is greater than a first threshold volume which will cause stress migration in at least one of the three conductive vias.
3. The method of claim 1 further comprising:
determining whether an area of the first conductive bus is greater than a first threshold area which will cause stress migration in at least one of the three conductive vias.
4. The method of claim 1 further comprising:
determining the first critical distance based on at least one of the width and a length of of the first conductive bus.
5. The method of claim 1 further comprising:
determining whether a volume of the second conductive bus is greater than a second threshold volume which will cause stress migration in at least one of the three conductive vias.
6. The method of claim 1 further comprising:
determining whether an area of the second conductive bus is greater than a second threshold area which will cause stress migration in at least one of the three conductive vias.
7. The method of claim 1 further comprising:
determining the second critical distance based on at least one of the width and a length of one of the second conductive bus.
8. The method of claim 1 wherein
the first conductive bus has a first length,
the second conductive bus has a second length, and
at least one of the first length and the second length is greater than a predetermined length.
9. The method of claim 1 wherein
the first conductive bus is in a first layer of an integrated circuit, and
the second conductive bus is in a second layer of the integrated circuit.
10. The method of claim 1 wherein
the first conductive bus and the second conductive bus are in a same layer of an integrated circuit.
11. A method for determining placement of vias in a semiconductor device comprising:
for a conductive bridge in the semiconductor device:
determining a width of a first conductive bus;
determining a width of a second conductive bus;
determining a width of the conductive bridge, wherein the conductive bridge is conductively coupled to the first and second conductive buses; and
when the width of the conductive bridge is less than the width of the first conductive bus and the width of the second conductive bus, forming three conductive vias in the conductive bridge,
wherein a middle via of the three conductive vias is positioned a first distance along the conductive bridge from the first conductive bus that is less than a first vacancy migration critical distance, and wherein the middle via is positioned a second distance along the conductive bridge from the second conductive bus that is less than a second vacancy migration critical distance.
12. The method of claim 11 further comprising:
determining whether a volume of the first conductive bus is greater than a first threshold volume which will cause stress migration in at least one of the three conductive vias.
13. The method of claim 11 further comprising:
determining whether an area of the first conductive bus is greater than a first threshold area which will cause stress migration in at least one of the three conductive vias.
14. The method of claim 11 further comprising:
determining the first critical distance based on at least one of the width and a length of the first conductive bus.
15. The method of claim 11 further comprising:
determining whether a volume of the second conductive bus is greater than a second threshold volume which will cause stress migration in at least one of the three conductive vias.
16. The method of claim 11 further comprising:
determining whether an area of the second conductive bus is greater than a second threshold area which will cause stress migration in at least one of the three conductive vias.
17. The method of claim 11 further comprising:
determining the second critical distance based on at least one of the width and a length of one of the second conductive bus.
18. The method of claim 11 wherein
the first conductive bus has a first length,
the second conductive bus has a second length, and
at least one of the first length and the second length is greater than a predetermined length.
19. The method of claim 11 wherein
the first conductive bus is in a first layer of an integrated circuit, and
the second conductive bus is in a second layer of the integrated circuit.
20. The method of claim 11 wherein
the first conductive bus and the second conductive bus are in a same layer of an integrated circuit.