IP Library Granted Patent US 9,111,901
Granted Patent B2
US 9,111,901 · App. 14/287,142 · Granted Aug 18, 2015

Methods for bonding a die and a substrate

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,111,901
App. No.
14/287,142
Granted
Aug 18, 2015
Kind
B2
Abstract

Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Claims (36)

1. A method for forming a semiconductor device that includes a die and a substrate, the method comprising:

forming a barrier layer over a first surface of a portion of the substrate;

forming a palladium layer over the barrier layer;

forming a first gold layer over a first surface of the die; and

bonding the die and the substrate by

pressing together the die and the substrate such that the first gold layer and the palladium layer are between the die and the substrate, and

heating the first gold layer and the palladium layer to form a die attach layer between the die and the substrate, the die attach layer comprising a gold interface layer that includes gold and a plurality of first precipitates in the gold, wherein each of the first precipitates comprises a combination of nickel, cobalt, palladium, gold, and silicon.

2. The method of forming a semiconductor device according to claim 1 , wherein the barrier layer comprises cobalt and nickel.

3. The method of forming a semiconductor device according to claim 1 , wherein forming the barrier layer comprises forming the barrier layer to have a thickness in a range of 1 micron to 10 microns.

4. The method of forming a semiconductor device according to claim 1 , wherein forming the palladium layer comprises forming the palladium layer to have a thickness in a range of 0.03 micron to 0.5 micron.

5. The method for forming a semiconductor device according to claim 1 , wherein forming the first gold layer comprises forming the first gold layer to have a thickness in a range of 1.2 microns to 2.0 microns.

6. The method for forming a semiconductor device according to claim 1 , wherein forming the first gold layer comprises forming the first gold layer to have a thickness of up to 2.5 microns.

7. The method of forming a semiconductor device according to claim 1 , further comprising:

forming a second gold layer over the palladium layer prior to bonding the die and the substrate.

8. The method for forming a semiconductor device according to claim 7 , wherein forming the second gold layer comprises forming the second gold layer to have a thickness in a range of at least 0.03 microns.

9. The method for forming a semiconductor device according to claim 1 , wherein heating the first gold layer and the palladium layer comprises heating the substrate and the die to a temperature of 430 degrees Celsius or less.

10. The method for forming a semiconductor device according to claim 1 , wherein pressing together the die and the substrate comprises applying a force between the die and the substrate.

11. The method for forming a semiconductor device according to claim 1 , wherein bonding the die and the substrate further comprises scrubbing together the die and the substrate.

12. The method for forming a semiconductor device according to claim 1 , wherein the step of bonding is further characterized in that the die attach layer has a thickness in a range of 0.1 microns to 10 microns.

13. The method for forming a semiconductor device according to claim 1 , wherein the step of bonding is further characterized in that, after the step of bonding, the first gold layer is in contact with a silicon portion of the die.

14. The method for forming a semiconductor device according to claim 1 , further comprising:

coupling a plurality of leads to the substrate; and

forming electrical connections between the die and the plurality of leads.

15. The method for forming a semiconductor device according to claim 14 , further comprising:

coupling insulating layers between the primary portion of the substrate and the leads.

16. A method for forming a semiconductor device that includes a die and a substrate, the method comprising:

pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate; and

performing a bonding operation to form a die attach layer between the die and the substrate, the die attach layer comprising a gold interface layer that includes gold and a plurality of first precipitates in the gold, wherein each of the first precipitates comprises a combination of nickel, cobalt, palladium, gold, and silicon.

17. The method for forming a semiconductor device according to claim 16 , further comprising the steps, performed before pressing together the die and the substrate, of:

forming a barrier layer comprising cobalt and nickel over a first surface of a portion of the substrate;

forming a palladium layer over the barrier layer; and

forming the first gold layer over a first surface of the die.

18. The method for forming a semiconductor device according to claim 17 , wherein forming the first gold layer comprises forming the first gold layer to have a thickness up to 2.5 microns.

19. The method of forming a semiconductor device according to claim 17 , further comprising:

forming a second gold layer over the palladium layer prior to pressing together the die and the substrate.

20. The method for forming a semiconductor device according to claim 19 , wherein forming the second gold layer comprises forming the second gold layer to have a thickness of at least 0.03 microns.

Assignments (25)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →