IP Library Granted Patent US 9,214,447
Granted Patent B2
US 9,214,447 · App. 14/277,061 · Granted Dec 15, 2015

Non-leaded type semiconductor package and method of assembling same

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Quick Facts
Patent No.
US 9,214,447
App. No.
14/277,061
Granted
Dec 15, 2015
Kind
B2
Abstract

A no-lead type semiconductor package has a mold cap that forms a mold body. The corners of the mold body are reinforced with mold columns such that the corners have rounded protrusions and do not form 90° angles. The mold columns prevent the corner pads from peeling.

Claims (23)

1. A semiconductor package, comprising:

a die flag having an upper surface and a lower surface;

a semiconductor die attached on the upper surface of the die flag;

a plurality of leads surrounding the die flag, wherein each of the leads has a top surface and a bottom surface opposite to the top surface, and the top surface is electrically connected with the semiconductor die with a bond wire; and

a mold cap that covers the semiconductor die, bond wires, and at least a portion of each of the leads, wherein the mold cap comprises a generally rectangular mold body, and wherein the mold body has reinforced corners comprising mold columns that protrude from each of said corners,

wherein the mold columns are formed at the corners of the mold body such that the corners of the mold body are rounded.

2. The semiconductor package of claim 1 , wherein the mold cap is formed of an epoxy resin material.

3. The semiconductor package of claim 1 , wherein each of the plurality of mold columns has a height equal to or less than a height of the mold body.

4. The semiconductor package of claim 1 , wherein the bottom surface of each of the leads is exposed.

5. The semiconductor package of claim 4 , wherein the lower surface of the die flag is exposed.

6. The semiconductor package of claim 4 , wherein distal ends of the leads are exposed along the side edges of the mold body.

7. The semiconductor package of claim 1 , wherein the mold columns prevent the corners from forming a 90° angle.

8. A method of assembling a semiconductor package, comprising:

providing a lead frame including a die flag and a plurality of leads surrounding the die flag, wherein each of the leads has a top surface and a bottom surface opposite to the top surface;

bonding a semiconductor die on a top surface of the die flag;

electrically connecting bonding pads on a top surface of the semiconductor die with the top surfaces of the leads with bond wires;

forming a mold cap by encapsulating the die flag, the semiconductor die, the bond wires and at least a portion of each of the leads with a mold compound, wherein the mold cap comprises a generally rectangular mold body with reinforced corners comprising mold columns that protrude from each of said corners; and

performing a trim and form operation that removes portions of the lead frame that extend beyond said mold cap,

wherein the lead frame further includes a plurality of rails that surround the die flag and from which the leads extend toward the die flag, wherein each of the rails is parallel to a respective one of (i) a side of the die flag, (ii) a plurality of tie bars that extend from corners of the die flag to the rails, and (iii) a plurality of tie bar pads that join respective ones of the tie bars with the rails at corners of the lead frame, and wherein the trim and form operation comprises removing the rails and tie bar pads.

9. The method of assembling a semiconductor package of claim 8 , wherein the rails and tie bar pads are removed by punching.

10. The method of assembling a semiconductor package of claim 9 , wherein a first punch operation is performed to remove the rails and a second punch operation is performed to remove the tie bar pads.

11. The method of assembling a semiconductor package of claim 9 , wherein the semiconductor package is a punch QFN package.

12. The method of assembling a semiconductor package of claim 8 , wherein each of the plurality of mold columns has a height equal to or less than a height of the mold body.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2014
From: BAI, ZHIGANG; WANG, ZHIJIE; YAO, JINZHONG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032883/0465 →