IP Library Granted Patent US 9,000,518
Granted Patent B2
US 9,000,518 · App. 14/261,231 · Granted Apr 7, 2015

Semiconductor device and related fabrication methods

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Quick Facts
Patent No.
US 9,000,518
App. No.
14/261,231
Granted
Apr 7, 2015
Kind
B2
Abstract

Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions. In one or more embodiments, the vertical drift regions and buried lateral drift region have the same conductivity type, wherein a body region of the opposite conductivity type overlies the buried lateral drift region between the vertical drift regions.

Claims (56)

1. A method of fabricating a transistor on an active region of semiconductor material having a first conductivity type, the method comprising:

forming a buried lateral drift region of semiconductor material having a second conductivity type within the active region;

forming a first vertical drift region of semiconductor material having the second conductivity type within the active region, wherein the first vertical drift region abuts the buried lateral drift region;

forming a second vertical drift region of semiconductor material having the second conductivity type within the active region, wherein the second vertical drift region abuts the buried lateral drift region;

forming a body region of semiconductor material overlying the buried lateral drift region between the first vertical drift region and the second vertical drift region;

forming a gate structure overlying the first vertical drift region; and

forming a drain region of semiconductor material within the second vertical drift region.

2. A method of fabricating a transistor on an active region of semiconductor material having a first conductivity type, the method comprising:

forming a lateral drift region having the second conductivity type within the active region;

forming a body region of semiconductor material having the first conductivity type within the lateral drift region, wherein a depth of the body region is less than a depth of the lateral drift region resulting in a buried lateral drift region underlying the body region;

forming a first vertical drift region of semiconductor material having the second conductivity type within the active region, wherein the first vertical drift region abuts the buried lateral drift region; and

forming a second vertical drift region of semiconductor material having the second conductivity type within the active region, wherein the second vertical drift region abuts the buried lateral drift region.

3. The method of claim 2 , wherein the body region abuts the first vertical drift region and the second vertical drift region.

4. The method of claim 2 , further comprising forming a source region of semiconductor material having the second conductivity type, wherein at least a portion of the body region is laterally between the source region and the first vertical drift region.

5. The method of claim 4 , further comprising forming an isolation region of dielectric material between the source region and the second vertical drift region, wherein:

the isolation region overlies at least a second portion of the body region; and

the second portion of the body region overlies the buried lateral drift region.

6. method of claim 5 , further comprising:

forming a drain region of semiconductor material having the second conductivity type within the second vertical drift region;

forming an electrode structure overlying the isolation region; and

forming an electrical connection between the drain region and the electrode structure, wherein the isolation region is laterally between the source region and the drain region.

7. The method of claim 1 , further comprising:

forming a source region of semiconductor material having the second conductivity type within the body region proximate the gate structure, wherein the gate structure overlies a portion of the body region disposed between the source region and the first vertical drift region.

8. The method of claim 7 , further comprising:

forming an isolation region of dielectric material overlying the body region,

wherein the isolation region is disposed between the source region and the drain region.

9. The method of claim 1 , further comprising:

forming an isolation region of dielectric material overlying the body region; and

forming an electrode structure overlying the isolation region.

10. A method of fabricating a transistor on an active region of semiconductor material having a first conductivity type, the method comprising:

forming a lateral drift region having a second conductivity type within the active region;

forming a body region of semiconductor material having the first conductivity type within the lateral drift region, wherein a depth of the body region is less than a depth of the lateral drift region resulting in a buried lateral drift region underlying the body region;

forming a first vertical drift region of semiconductor material having the second conductivity type within the active region, wherein the first vertical drift region abuts the buried lateral drift region;

forming a second vertical drift region of semiconductor material having the second conductivity type within the active region, wherein the second vertical drift region abuts the buried lateral drift region;

forming a gate structure overlying the first vertical drift region; and

forming a source region of semiconductor material having the second conductivity type within the body region proximate the gate structure, wherein the gate structure overlies a portion of the body region disposed between the source region and the first vertical drift region.

11. The method of claim 10 , further comprising:

forming an isolation region of dielectric material overlying the body region; and

forming a drain region of semiconductor material having the second conductivity type within the second vertical drift region, wherein the isolation region is disposed between the source region and the drain region.

12. The method of claim 11 , further comprising:

forming an electrode structure overlying the isolation region; and

forming an electrical connection between the electrode structure and the drain region.

13. The method of claim 10 , wherein the body region abuts the first vertical drift region and the second vertical drift region.

14. A method of fabricating a transistor on an active region of semiconductor material having a first conductivity type, the method comprising:

forming a buried lateral drift region of semiconductor material having a second conductivity type within the active region;

forming a first vertical drift region of semiconductor material having the second conductivity type within the active region, wherein the first vertical drift region abuts the buried lateral drift region;

forming a second vertical drift region of semiconductor material having the second conductivity type within the active region, wherein the second vertical drift region abuts the buried lateral drift region;

forming a body region of semiconductor material having the first conductivity type within the active region overlying the buried lateral drift region;

forming a gate structure overlying the first vertical drift region; and

forming a source region of semiconductor material having the second conductivity type within the body region proximate the gate structure, wherein the gate structure overlies a portion of the body region disposed between the source region and the first vertical drift region.

15. The method of claim 14 , further comprising forming a drain region of semiconductor material within the second vertical drift region, the drain region having the second conductivity type.

16. The method of claim 15 , further comprising:

forming an isolation region of dielectric material between the source region and the drain region; and

forming an electrode structure overlying the isolation region, wherein the isolation region is disposed between the electrode structure and the body region.

17. The method of claim 16 , further comprising forming an electrical connection between the electrode structure and the drain region.

18. The method of claim 14 , wherein the body region abuts the first vertical drift region and the second vertical drift region.

Assignments (16)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2014
From: YANG, HONGNING; LIN, XIN; ZUO, JIANG-KAI
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 032752/0632 →