Methods and structures for split gate memory cell scaling with merged control gates
A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.
1. A method of making a memory device using a substrate, comprising:
forming a first select gate over the substrate;
forming a second select gate over the substrate;
forming a first doped region in the substrate between the first select gate and the second select gate, wherein a top surface of the first doped region is substantially coplanar with a top surface of the substrate;
forming a control gate over the first doped region, between the first doped region and the first select gate, and between the first doped region and the second select gate; and
forming a charge storage layer over the substrate including over the first doped region prior to forming the control gate.
2. The method of claim 1 , wherein the charge storage layer comprises nanocrystals.
3. The method of claim 1 , wherein the forming the first doped region comprises:
forming a first sidewall spacer on the first select gate on a side nearest the second select gate;
forming a second sidewall spacer on the second select gate on a side nearest the first select gate;
implanting into the substrate using the first sidewall spacer and the second sidewall spacer as a mask to form the first doped region.
4. The method of claim 3 , further comprising removing the first sidewall spacer and the second sidewall spacer to leave a first space adjacent to the first select gate and a second space adjacent to the second select gate.
5. The method of claim 4 , wherein the forming the control gate comprises forming a conductive material in the first space, the second space, and over the first doped region.
6. The method of claim 5 , wherein the forming the control gate further comprises forming the control gate over a portion of the first select gate and a portion of the second select gate.
7. The method of claim 6 , wherein the forming the charge storage layer comprises forming a layer comprising nanocrystals over the substrate prior to forming the control gate.
8. The method of claim 1 , further comprising forming a gate dielectric on the substrate prior to forming the first select gate and the second select gate.
9. The method of claim 1 , wherein the forming the first doped region comprises:
forming a masking layer over the substrate, wherein the masking layer has an opening over a region between the first select gate and the second select gate; and
performing an implant into the substrate through the opening to form the first doped region.
10. A method of forming a memory device using a substrate, comprising:
forming a first select gate and a second select gate separated from the first select gate structure by a space;
forming a doped region centered between the first select gate and the second select gate in the space, wherein the doped region has a top surface substantially coplanar with a top surface of the substrate;
forming a control gate adjacent to the first select gate and the second select gate and over the doped region; and
forming a charge storage layer over the substrate including over the doped region prior to forming the control gate.
11. The method of claim 10 , wherein the forming the doped region comprises:
forming a first sidewall spacer on the first select gate on a side nearest the second select gate;
forming a second sidewall spacer on the second select gate on a side nearest the first select gate;
implanting into the substrate using the first sidewall spacer and the second sidewall spacer as a mask to form the doped region.