IP Library Granted Patent US 9,528,883
Granted Patent B2
US 9,528,883 · App. 14/258,629 · Granted Dec 27, 2016

Temperature sensor circuitry with scaled voltage signal

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Quick Facts
Patent No.
US 9,528,883
App. No.
14/258,629
Granted
Dec 27, 2016
Kind
B2
Abstract

Temperature sensing circuitry implemented on a semiconductor integrated circuit that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensing circuitry converts a voltage signal that is proportional to the temperature to a frequency-based signal, which is converted to a digital bit value. A scalar factor is applied to another voltage signal that is inversely proportional to the temperature to produce a scaled voltage signal. The scaled voltage signal is converted to a second frequency-based signal, which is converted to a digital bit value, and then the two digital bit values are compared. The temperature is determined when the digital bit values substantially match.

Claims (53)

1. A system for determining a temperature of a location in an integrated circuit, comprising:

first circuitry, in proximity to the location in the integrated circuit, configured to adjust first and second output voltages as a function of its operating temperature;

second circuitry configured to convert the first and second output voltages to a first voltage signal that is proportional to the operating temperature, the second circuitry comprising a first current mirror circuit with a first input coupled to receive the first output voltage from the first circuitry and a second input coupled to receive the second output voltage from the first circuitry, wherein the first current mirror circuit converts a difference between the first and second output voltages into the first voltage signal that is proportional to the operating temperature;

third circuitry configured to convert the second output voltage to a second voltage signal that is inversely proportional to the operating temperature;

fourth circuitry configured to apply one of a plurality of selectable scalar factors to the second voltage signal to produce a scaled voltage signal; and

fifth circuitry configured to determine the temperature of the location in the integrated circuit when the scaled voltage signal is substantially equal to the first voltage signal.

2. The system as recited in claim 1 , wherein the third circuitry further comprises a second current mirror circuit with a third input coupled to receive the second output voltage from the first circuitry, wherein the fourth circuitry further comprises a circuit array configured to multiply the second voltage signal by one of the plurality of selectable scalar factors to produce the scaled voltage signal.

3. The system as recited in claim 2 , wherein the fifth circuitry further comprises:

a first ring oscillator configured to convert the first voltage signal that is proportional to the operating temperature to a first frequency-based signal;

a first counter configured to convert the first frequency-based signal to a first digital bit value;

a second ring oscillator configured to convert the scaled voltage signal to a second frequency-based signal;

a second counter configured to convert the second frequency-based signal to a second digital bit value; and

circuitry configured to compare the first and second digital bit values.

4. The system as recited in claim 2 , wherein the fifth circuitry further comprises sixth circuitry configured to multiply the second voltage signal by an increment of one of the plurality of selectable scalar factors when the first and second digital bit values do not match.

5. The system as recited in claim 3 , wherein the fifth circuitry further comprises circuitry configured to output the temperature when the first and second digital bit values substantially match.

6. The system as recited in claim 3 , wherein the first and second ring oscillators are the same ring oscillator, and wherein the first and second counters are the same counter.

7. The system as recited in claim 1 , wherein the first circuitry further comprises:

a first set of one or more diodes having a first emitter injection area, the first set of the one or more diodes outputting the first output voltage; and

a second set of one or more diodes having a second emitter injection area, the second set of the one or more diodes outputting the second output voltage, wherein the second emitter injection area is greater than the first emitter injection area.

8. A method for determining a temperature of a location in an integrated circuit, comprising:

converting a first voltage signal that is proportional to the temperature to a first frequency-based signal;

converting the first frequency-based signal to a first digital bit value;

applying a first scalar factor to a second voltage signal that is inversely proportional to the temperature to produce a first scaled voltage signal, wherein the first and second voltage signals are generated from first and second voltages outputted by circuitry resident at the location in the integrated circuit;

converting the first scaled voltage signal to a second frequency-based signal;

converting the second frequency-based signal to a second digital bit value;

comparing the first and second digital bit values; and

outputting the temperature when the first and second digital bit values substantially match.

9. The method as recited in claim 8 , further comprising:

applying a second scalar factor to the second voltage signal that is inversely proportional to the temperature to produce a second scaled voltage signal when the first and second digital bit values do not substantially match;

converting the second scaled voltage signal to a third frequency-based signal;

converting the third frequency-based signal to a third digital bit value;

comparing the first and third digital bit values; and

outputting the temperature when the first and third digital bit values substantially match.

10. The method as recited in claim 8 , wherein the first voltage signal that is proportional to the temperature is a difference between the first and second voltages.

11. The method as recited in claim 8 , wherein the outputting of the temperature further comprises determining the temperature that corresponds to the applied first scalar factor.

12. The method as recited in claim 9 , wherein the outputting of the temperature further comprises determining the temperature that corresponds to the applied second scalar factor.

13. A system for determining a temperature of a location in an integrated circuit, comprising:

a first set of circuit elements outputting a first output voltage;

a second set of circuit elements outputting a second output voltage, wherein the first and second sets of circuit elements are resident at the location in the integrated circuit, wherein the first and second output voltages independently vary as a function of an operating temperature of the integrated circuit at the location, wherein the first and second output voltages are not equal;

a first current mirror circuit with a first input coupled to receive the first output voltage and a second input coupled to receive the second output voltage, wherein the first current mirror circuit converts a difference between the first and second output voltages into a first voltage signal that is proportional to the operating temperature;

a second current mirror circuit with a third input coupled to receive the second output voltage, wherein the second current mirror circuit further comprises a circuit array configured to multiply the second voltage by one of a plurality of selectable scalar factors to produce a scaled voltage signal that is inversely proportional to the operating temperature; and

circuitry configured to determine the temperature of the location in the integrated circuit when the scaled voltage signal is substantially equal to the first voltage signal.

14. The system as recited in claim 13 , wherein the circuitry configured to determine the temperature of the location in the integrated circuit when the scaled voltage signal is substantially equal to the first voltage signal further comprises:

a first ring oscillator configured to convert the first voltage signal that is proportional to the operating temperature to a first frequency-based signal;

a first counter configured to convert the first frequency-based signal to a first digital bit value;

a second ring oscillator configured to convert the scaled voltage signal to a second frequency-based signal;

a second counter configured to convert the second frequency-based signal to a second digital bit value; and

circuitry configured to compare the first and second digital bit values.

15. The system as recited in claim 14 , wherein the circuitry configured to determine the temperature of the location in the integrated circuit when the scaled voltage signal is substantially equal to the first voltage signal further comprises circuitry configured to cause the circuit array to multiply the second voltage by an increment of one of the plurality of selectable scalar factors when the first and second digital bit values do not match.

16. The system as recited in claim 15 , wherein the circuitry configured to determine the temperature of the location in the integrated circuit when the scaled voltage signal is substantially equal to the first voltage signal further comprises circuitry configured to output the temperature when the first and second digital bit values substantially match.

17. The system as recited in claim 14 , wherein the first and second ring oscillators are the same ring oscillator, and wherein the first and second counters are the same counter.

18. The system as recited in claim 13 , wherein the first set of circuit elements further comprises a first set of one or more diodes having a first emitter injection area, the first set of the one or more diodes outputting the first output voltage, wherein the second set of circuit elements further comprises a second set of one or more diodes having a second emitter injection area, the second set of the one or more diodes outputting the second output voltage, wherein the second emitter injection area is greater than the first emitter injection area.

19. The system as recited in claim 13 , wherein the circuitry configured to determine the temperature of the location in the integrated circuit when the scaled voltage signal is substantially equal to the first voltage signal further comprises circuitry for determining the temperature that corresponds to the one of the plurality of selectable scalar factors that produces the scaled voltage signal that is substantially equal to the first voltage signal.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2014
From: RAMARAJU, RAVINDRARAJ; BEARDEN, DAVID R.; MANICKAVASAKAM, SUNITHA; MOORAKA, VENKATARAM M.; SANCHEZ, HECTOR
To: FREESCALE SEMICONDUCTOR, INC.
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