Imminent read failure detection based upon changes in error voltage windows for NVM cells
View Patent ↗Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.
1. A method for detecting imminent read failures for a non-volatile memory (NVM) system, comprising:
at a first time:
performing a low read voltage sweep for an array of non-volatile memory (NVM) cells to determine a first low error voltage level;
performing a high read voltage sweep for the array of NVM cells to determine a first high error voltage level;
defining a first voltage window based upon a difference between the first high error voltage level and the first low error voltage level;
at a second time:
performing a low read voltage sweep for the array of NVM cells to determine a second low error voltage level;
performing a high read voltage sweep for the array of NVM cells to determine a second high error voltage level; and
defining a second voltage window based upon a difference between the second high error voltage level and the second low error voltage level;
comparing a difference between the first voltage window and the second voltage window to a voltage difference threshold value; and
indicating an imminent read failure for the array of NVM cells based upon the comparison.
2. The method of claim 1 , further comprising incrementally decreasing a read voltage level from a normal read voltage level to perform the low voltage sweeps and incrementally increasing the read voltage level from the normal read voltage level for the high voltage sweeps, the normal read voltage level being used for non-diagnostic read operations for the array of NVM cells.
3. The method of claim 2 , wherein the incrementally decreasing comprises incrementally decreasing the voltage level from the normal read voltage level by between 0.05 to 0.10 volt steps, and the incrementally increasing comprises incrementally increasing the voltage level from the normal read voltage level by between 0.05 to 0.10 volt steps.
4. The method of claim 3 , wherein the normal read voltage level is 4.5 volts, wherein the incrementally decreasing uses a 0.10 volt step, and wherein the incrementally increasing uses a 0.10 volt step.
5. The method of claim 2 , wherein each performing step comprises performing read and error correction operations for the array of NVM cells at each read voltage level used for the read voltage sweep until the uncorrectable bit error is detected and recording a read voltage level associated with the uncorrectable bit error as the error voltage level.
6. The method of claim 1 , further comprising accessing a calibration table to determine expected voltage window values associated with the first and second times and using a difference between the expected voltage window values to determine the voltage difference threshold value.
7. The method of claim 1 , further comprising using one or more error correction code (ECC) routines for the periodically performing steps.
8. The method of claim 7 , wherein the error correction routines are configured to identify a double-bit error as an uncorrectable read error.
9. The method of claim 1 , wherein the indicating step comprises storing within a data storage medium a flag indicating whether or not an imminent read failure condition has been detected.
10. The method of claim 1 , wherein the indicating step comprises outputting a failure indicator signal.
11. The method of claim 1 , wherein the first time and the second time comprise timestamps.
12. The method of claim 1 , wherein the first failure time and the second time comprise counted values.
13. The method of claim 12 , wherein the counted value comprises at least one the following: power-up events for the NVM system, operational cycles for the NVM system, automobile starts for an automobile within which the NVM system is operating, or odometer readings for an automobile within which the NVM system is operating.
14. A non-volatile memory (NVM) system having imminent read failure detection, comprising:
a non-volatile memory (NVM) including an array of NVM cells;
a memory management unit coupled to the array of NVM cells;
a controller within the memory management unit coupled to the NVM and configured to
determine from a diagnostic mode run at a first time a first voltage window associated with a difference between a first low error voltage level determined from a low read voltage sweep and a first high voltage error level determined from a high read voltage sweep, to determine from the diagnostic mode run at a second time a second voltage window associated with a difference between a second low error voltage level determined from a low read voltage sweep and a second high voltage error level determined from a high read voltage sweep, to compare a difference between the first and second voltage windows to a voltage difference threshold value, and to indicate an imminent read failure for the array of NVM cells based upon the comparison.
15. The NVM system of claim 14 , further comprising a data storage medium configured to store a calibration table including expected voltage window values associated with time values, and wherein the controller is further configured to use the calibration table to obtain expected voltage window values associated with the first and second times and to use a difference between the expected voltage window values to determine the voltage difference threshold value.
16. The NVM system of claim 14 , wherein the memory management unit further comprises error correction code (ECC) logic configured to run one or more ECC routines, and wherein the controller is further configured to use results from the ECC logic as indications of uncorrectable read errors.
17. The NVM system of claim 14 , wherein the controller is further configured to store within the data storage medium a flag indicating whether or not an imminent read failure condition has been detected.
18. The NVM system of claim 14 , wherein the controller is further configured to output a failure indicator signal.
19. The NVM system of claim 14 , wherein the controller is configured to incrementally decrease a read voltage level from a normal read voltage level for the low voltage sweeps and to incrementally increase the read voltage level from the normal read voltage level for the high voltage sweeps, the normal read voltage level being used for non-diagnostic read operations for the array of NVM cells.
20. The NVM system of claim 19 , wherein the controller is configured to use 0.05 to 0.10 volt steps for low and high voltage sweeps.