IP Library Granted Patent US 9,331,642
Granted Patent B2
US 9,331,642 · App. 14/318,036 · Granted May 3, 2016

Monolithic transistor circuits with tapered feedback resistors, RF amplifier devices, and methods of manufacture thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,331,642
App. No.
14/318,036
Granted
May 3, 2016
Kind
B2
Abstract

Embodiments of an integrated resistor may be incorporated into monolithic transistor circuits and packaged RF amplifier devices. An embodiment of an integrated resistor includes a semiconductor substrate and a resistor formed over the top surface of the semiconductor substrate from resistive material. The resistor includes at least first and second resistive sections. The first resistive section is tapered so that the first resistive section widens toward an input end of the resistor. The second resistive section is coupled in series with the first resistive section. According to a further embodiment, the second resistive section also is tapered so that the second resistive section widens toward an output end of the resistor. According to another further embodiment, a third resistive section with one or more meanders is coupled in series between the first and second resistive sections.

Claims (119)

1. An integrated resistor comprising:

a semiconductor substrate having a top surface; and

a resistor formed over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the resistor includes

an input end,

an output end,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 5 percent to 60 percent of the first width, and

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, wherein the second resistive section has a third width at the first end of the second resistive section, and a fourth width at the second end of the second resistive section, wherein the fourth width is at least 5 percent greater than the third width, and wherein the second end of the second resistive section corresponds to the output end of the resistor.

2. The integrated resistor of claim 1 , wherein a distance between sides of the first resistive section narrows along arcs between the first width and the second width.

3. The integrated resistor of claim 1 , wherein the first end of the second resistive section is directly connected to the second end of the first resistive section.

4. The integrated resistor of claim 1 , wherein the first end of the second resistive section is connected to the second end of the first resistive section through one or more intervening conductive structures.

5. An integrated resistor comprising:

a semiconductor substrate having a top surface; and

a resistor formed over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the resistor includes

an input end,

an output end,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 5 percent to 60 percent of the first width,

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first and second lengths are substantially parallel with a primary axis of the resistor, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, and the second end of the second resistive section corresponds to the output end of the resistor, and

a third resistive section coupled in series between the first resistive section and the second resistive section, wherein the third resistive section is defined by a first distance between a first end of the third resistive section and a second end of the third resistive section, wherein the first distance runs parallel with the primary axis of the resistor, and wherein the third resistive section includes one or more meander sections, wherein each meander section includes one or more resistive sub-sections that are not substantially parallel with the primary axis of the resistor, and a path length of resistive material forming the third resistive section is greater than the first distance.

6. The integrated resistor of claim 1 , wherein a distance between sides of the second resistive section widens along arcs between the third width and the fourth width.

7. The integrated resistor of claim 5 , wherein the second resistive section has a third width at the first end of the second resistive section, and a fourth width at the second end of the second resistive section, wherein the fourth width is substantially equal to the third width.

8. The integrated resistor of claim 5 , wherein each meander section has a serpentine shape.

9. The integrated resistor of claim 5 , wherein the path length is in a range of 150 percent to 500 percent of the first distance.

10. An integrated resistor comprising:

a semiconductor substrate having a top surface; and

a resistor formed over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the resistor includes

an input end,

an output end,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 2 percent to 80 percent of the first width, and

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, the second end of the second resistive section corresponds to the output end of the resistor, and wherein the second end of the second resistive section has a third width that is at least 5 percent greater than the second width.

11. The integrated resistor of claim 10 , wherein the first and second lengths are substantially parallel with a primary axis of the resistor, and wherein the resistor further comprises:

a third resistive section coupled in series between the first resistive section and the second resistive section, wherein the third resistive section is defined by a first distance between a first end of the third resistive section and a second end of the third resistive section, wherein the first distance runs parallel with the primary axis of the resistor, and wherein the third resistive section includes one or more meander sections, wherein each meander section includes one or more resistive sub-sections that are not substantially parallel with the primary axis of the resistor, and a path length of resistive material forming the third resistive section is greater than the first distance.

12. An integrated resistor comprising:

a semiconductor substrate having a top surface; and

a resistor formed over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the resistor includes

an input end,

an output end,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 2 percent to 80 percent of the first width,

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, and the second end of the second resistive section corresponds to the output end of the resistor, wherein the first and second lengths are substantially parallel with a primary axis of the resistor; and

a third resistive section coupled in series between the first resistive section and the second resistive section, wherein the third resistive section is defined by a first distance between a first end of the third resistive section and a second end of the third resistive section, wherein the first distance runs parallel with the primary axis of the resistor, and wherein the third resistive section includes one or more meander sections, wherein each meander section includes one or more resistive sub-sections that are not substantially parallel with the primary axis of the resistor, and a path length of resistive material forming the third resistive section is greater than the first distance.

13. The integrated resistor of claim 12 , wherein the second resistive section has a third width at the first end of the second resistive section, and a fourth width at the second end of the second resistive section, wherein the fourth width is at least 5 percent greater than the third width.

14. A monolithic transistor circuit comprising:

a semiconductor substrate;

a transistor formed in and over the semiconductor substrate, wherein the transistor includes a first current carrying terminal, a second current carrying terminal, a variable-conductivity channel between the first and second current carrying terminals, and a control terminal; and

a feedback circuit coupled between the first current carrying terminal and the control terminal, wherein the feedback circuit includes

an integrated feedback resistor formed over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the integrated feedback resistor includes

an input end coupled to the first current carrying terminal,

an output end coupled to the control terminal,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the integrated feedback resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 5 percent to 60 percent of the first width, and

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, and the second end of the second resistive section corresponds to the output end of the integrated feedback resistor, and

wherein the control terminal is coupled to a first conductive pad proximate to a top surface of the monolithic transistor circuit, the first current carrying terminal is coupled to a second conductive pad proximate to the top surface of the monolithic transistor circuit, and a total distance between the input and output ends of the integrated feedback resistor is less than or equal to a distance between the first and second conductive pads.

15. The monolithic transistor circuit of claim 14 , wherein the feedback circuit further comprises:

a capacitor coupled in series with the integrated feedback resistor.

16. The monolithic transistor circuit of claim 14 , wherein the one or more layers of resistive material are selected from polysilicon, tungsten silicide, and another material having a sheet resistivity in a range of 1.0 to 100 Ohms per square.

17. The monolithic transistor circuit of claim 14 , wherein the first end of the second resistive section is directly connected to the second end of the first resistive section.

18. A monolithic transistor circuit comprising:

a semiconductor substrate;

a transistor formed in and over the semiconductor substrate, wherein the transistor includes a first current carrying terminal, a second current carrying terminal, a variable-conductivity channel between the first and second current carrying terminals, and a control terminal; and

a feedback circuit coupled between the first current carrying terminal and the control terminal, wherein the feedback circuit includes

an integrated feedback resistor formed over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the integrated feedback resistor includes

an input end coupled to the first current carrying terminal,

an output end coupled to the control terminal,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the integrated feedback resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 5 percent to 60 percent of the first width, and

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, and the second end of the second resistive section corresponds to the output end of the integrated feedback resistor, and wherein the first end of the second resistive section is connected to the second end of the first resistive section through one or more intervening conductive structures.

19. A monolithic transistor circuit comprising:

a semiconductor substrate;

a transistor formed in and over the semiconductor substrate, wherein the transistor includes a first current carrying terminal, a second current carrying terminal, a variable-conductivity channel between the first and second current carrying terminals, and a control terminal; and

a feedback circuit coupled between the first current carrying terminal and the control terminal, wherein the feedback circuit includes

an integrated feedback resistor formed over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the integrated feedback resistor includes

an input end coupled to the first current carrying terminal,

an output end coupled to the control terminal,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the integrated feedback resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 5 percent to 60 percent of the first width,

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, and the second end of the second resistive section corresponds to the output end of the integrated feedback resistor, and wherein the first and second lengths are substantially parallel with a primary axis of the integrated feedback resistor, and

a third resistive section coupled in series between the first resistive section and the second resistive section, wherein the third resistive section is defined by a first distance between a first end of the third resistive section and a second end of the third resistive section, wherein the first distance runs parallel with the primary axis of the integrated feedback resistor, and wherein the third resistive section includes one or more meander sections, wherein each meander section includes one or more resistive sub-sections that are not substantially parallel with the primary axis of the integrated feedback resistor, and a path length of resistive material forming the third resistive section is greater than the first distance.

20. A packaged radio frequency (RF) amplifier device comprising:

a device substrate;

an input lead coupled to the device substrate;

an output lead coupled to the device substrate; and

a monolithic transistor circuit that includes

a semiconductor substrate,

a transistor formed in and over the semiconductor substrate, wherein the transistor includes a control terminal coupled to the input lead, a first current carrying terminal coupled to the output lead, a second current carrying terminal coupled to the device substrate, and a variable-conductivity channel between the first and second current carrying terminals, and

a feedback circuit coupled between the first current carrying terminal and the control terminal, wherein the feedback circuit includes

an integrated feedback resistor formed over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the integrated feedback resistor includes

an input end coupled to the first current carrying terminal,

an output end coupled to the control terminal,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the integrated feedback resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 5 percent to 60 percent of the first width, and

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, and the second end of the second resistive section corresponds to the output end of the integrated feedback resistor, and

wherein the control terminal is coupled to a first conductive pad proximate to a top surface of the semiconductor substrate, the first current carrying terminal is coupled to a second conductive pad proximate to the top surface of the semiconductor substrate, and a total distance between the input and output ends of the feedback resistor is less than or equal to a distance between the first and second conductive pads.

21. The packaged RF amplifier device of claim 20 , further comprising:

an input impedance matching circuit coupled to the device substrate between the input lead and the control terminal; and

an output impedance matching circuit coupled to the device substrate between the first current carrying terminal and the output lead.

22. The packaged RF amplifier device of claim 20 , wherein the first end of the second resistive section is directly connected to the second end of the first resistive section.

23. The packaged RF amplifier device of claim 20 , wherein the first end of the second resistive section is connected to the second end of the first resistive section through one or more intervening conductive structures.

24. The packaged RF amplifier device of claim 20 , wherein the first and second lengths are substantially parallel with a primary axis of the integrated feedback resistor, and wherein the integrated feedback resistor further comprises:

a third resistive section coupled in series between the first resistive section and the second resistive section, wherein the third resistive section is defined by a first distance between a first end of the third resistive section and a second end of the third resistive section, wherein the first distance runs parallel with the primary axis of the integrated feedback resistor, and wherein the third resistive section includes one or more meander sections, wherein each meander section includes one or more resistive sub-sections that are not substantially parallel with the primary axis of the integrated feedback resistor, and a path length of resistive material forming the third resistive section is greater than the first distance.

25. A method of manufacturing a device that includes an integrated resistor, the method comprising:

forming a transistor in and over a semiconductor substrate, wherein the transistor includes a first current carrying terminal, a second current carrying terminal, a variable-conductivity channel between the first and second current carrying terminals, and a control terminal;

forming a resistor over the top surface of the semiconductor substrate from one or more portions of one or more layers of resistive material, wherein the resistor includes

an input end,

an output end,

a first resistive section having a first length defined between a first end of the first resistive section and a second end of the first resistive section, wherein the first end of the first resistive section corresponds to the input end of the resistor, and the first end of the first resistive section has a first width, and wherein the second end of the first resistive section has a second width in a range of 5 percent to 60 percent of the first width, and

a second resistive section coupled in series with the first resistive section, wherein the second resistive section has a second length defined between a first end of the second resistive section and a second end of the second resistive section, wherein the first end of the second resistive section is coupled to the second end of the first resistive section, and the second end of the second resistive section corresponds to the output end of the resistor;

electrically coupling the input end of the resistor to the first current carrying terminal;

electrically coupling the output end of the resistor to the control terminal;

forming first and second conductive pads proximate to a top surface of the semiconductor substrate, wherein a total distance between the input and output ends of the feedback resistor is less than or equal to a distance between the first and second conductive pads;

electrically coupling the control terminal to the first conductive pad; and

electrically coupling the first current carrying terminal to the second conductive pad.

26. The method of claim 25 , further comprising:

forming an integrated capacitor over the semiconductor substrate; and

electrically coupling the integrated capacitor in series with the resistor between the first current carrying terminal and the control terminal.

27. The method of claim 25 , further comprising:

coupling an input lead and an output lead to a device substrate;

attaching the semiconductor substrate to a top surface of the device substrate;

electrically coupling the input lead to the control terminal of the transistor; and

electrically coupling the first current carrying terminal to the output lead.

28. The method of claim 27 , further comprising:

attaching one or more isolation structures to the top surface of the device substrate, wherein the input lead is attached to a first portion of the isolation structure, and the output lead is attached to a second portion of the isolation structure; and

attaching a lid over portions of the input lead, the output lead, the isolation structure, and the semiconductor substrate to form an air cavity device package.

29. The method of claim 27 , further comprising:

covering portions of the input lead, the output lead, and the semiconductor substrate with molding compound to form an overmolded device package.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2015
From: MUSA, SARMAD K.; MIN, SEUNGKEE; SZYMANOWSKI, MARGARET A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 035034/0232 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →