IP Library Granted Patent US 9,673,164
Granted Patent B2
US 9,673,164 · App. 14/261,899 · Granted Jun 6, 2017

Semiconductor package and system with an isolation structure to reduce electromagnetic coupling

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Quick Facts
Patent No.
US 9,673,164
App. No.
14/261,899
Granted
Jun 6, 2017
Kind
B2
Abstract

A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling is presented. The semiconductor device has a substrate on which a first circuit and a second circuit with inputs and outputs are formed proximate to each other. An isolation structure of electrically conductive material is located between components of the first and second circuits, the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. The isolation structure may be positioned on or over exterior surfaces of the semiconductor device housing or inside the housing. In one embodiment, the isolation structure includes a first leg extending transverse to the surface of the substrate and a first cross member connected to and projecting from the first leg over the substrate.

Claims (112)

1. A semiconductor device comprising:

a substrate having a surface;

a first circuit on the substrate and comprising a plurality of electrical components;

a second circuit on the substrate and comprising another plurality of electrical components;

a housing coupled to the substrate, wherein the housing includes a major surface above the surface of the substrate, and an edge surface orthogonal to the major surface and the surface of the substrate, and wherein the housing encloses the first and second circuits;

first and second connectors that project outward from the edge surface of the housing, wherein the first connector is coupled to the first circuit, the second connector is coupled to the second circuit, and the first and second connectors are physically separated from each other by a first distance across a portion of the edge surface;

a ground connector that projects outward from the edge surface of the housing between the first and second connectors; and

an isolation structure having an elongated first cross member coupled to the housing, and spaced from and extending over the surface of the substrate between the first circuit and the second circuit, wherein a length of the first cross member is greater than a width of the first cross member, and an area of the first cross member is smaller than an area of the surface of the substrate, and wherein the isolation structure further includes a first leg coupled to the housing and extending transverse to the first cross member and to the surface of the substrate, wherein the first leg is directly connected to the ground connector, the first leg has a width dimension that is parallel to and smaller than the first distance between the first and second connectors, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

2. The semiconductor device as recited in claim 1 , wherein the isolation structure is formed of electrically conductive material.

3. The semiconductor device as recited in claim 1 , wherein the first cross member is located on the major surface of the housing.

4. The semiconductor device as recited in claim 1 , wherein the first cross member is within the housing.

5. The semiconductor device as recited in claim 1 , wherein the isolation structure further comprises a second leg extending transverse to the surface of the substrate and attached to the first cross member.

6. A semiconductor device comprising:

a substrate having a surface;

a first circuit on the substrate and comprising a plurality of electrical components;

a second circuit on the substrate and comprising another plurality of electrical components;

a housing coupled to the substrate, wherein the housing includes a major surface above the surface of the substrate, and an edge surface orthogonal to the major surface and the surface of the substrate, and wherein the housing encloses the first and second circuits;

first and second connectors that project outward from the housing, wherein the first connector is coupled to the first circuit, and the second connector is coupled to the second circuit;

a ground connector that projects outward from the edge surface of the housing between the first and second connectors; and

an isolation structure having a first cross member coupled to the housing, and spaced from and extending over the surface of the substrate between the first circuit and the second circuit, a first leg coupled to the housing and extending transverse to the first cross member and to the surface of the substrate, wherein the first leg is directly connected to the ground connector, and a second cross member spaced from and extending over the surface of the substrate, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

7. The semiconductor device as recited in claim 6 wherein the first cross member is electrically connected in common with the second cross member.

8. A semiconductor device comprising:

a substrate;

a first circuit on the substrate;

a second circuit on the substrate;

a housing coupled to the substrate, extending over and enclosing the first circuit and the second circuit, and comprising a major surface and first and second edge surfaces both abutting the major surface;

first and second connectors that project outward from the edge surface of the housing, wherein the first connector is coupled to the first circuit, the second connector is coupled to the second circuit, and the first and second connectors are physically separated from each other by a first distance across a portion of the edge surface;

a ground connector that projects outward from the housing and is located between the first and second connectors; and

an isolation structure comprising a first leg coupled to and proximate to the first edge surface and an elongated first cross member coupled to and proximate to the major surface and electrically connected to the first leg, wherein the first leg is directly connected to the ground connector, wherein the first leg has a width dimension that is parallel to and smaller than the first distance between the first and second connectors, wherein a length of the first cross member is greater than a width of the first cross member, and an area of the first cross member is smaller than an area of the surface of the substrate, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

9. The semiconductor device as recited in claim 8 , wherein the isolation structure further comprises a second leg formed on the second edge surface and electrically connected to the first cross member.

10. A semiconductor device comprising:

a substrate;

a first circuit on the substrate;

a second circuit on the substrate;

a housing coupled to the substrate, extending over and enclosing the first circuit and the second circuit, and comprising a major surface and first and second edge surfaces both abutting the major surface;

first and second connectors that project outward from the housing, wherein the first connector is coupled to the first circuit, and the second connector is coupled to the second circuit;

a ground connector that projects outward from the housing and is located between the first and second connectors; and

an isolation structure comprising

a first leg coupled to and proximate to the first edge surface,

a first cross member coupled to and proximate to the major surface and electrically connected to the first leg, and

a second cross member on the major surface and electrically coupled to the first cross member,

wherein the first leg is directly connected to the ground connector, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

11. A semiconductor device comprising:

a substrate;

a first circuit on the substrate;

a second circuit on the substrate;

a housing coupled to the substrate, extending over and enclosing the first circuit and the second circuit, and comprising a major surface and first and second edge surfaces both abutting the major surface;

first and second connectors that project outward from the housing, wherein the first connector is coupled to the first circuit, and the second connector is coupled to the second circuit;

a ground connector that projects outward from the housing and is located between the first and second connectors; and

an isolation structure comprising

a first leg coupled to and proximate to the first edge surface,

a first cross member coupled to and proximate to the major surface and electrically connected to the first leg,

an additional leg formed on one of the first edge surface and the second edge surface, and

a second cross member formed on the major surface and electrically connected to the additional leg,

wherein the first leg is directly connected to the ground connector, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

12. The semiconductor device as recited in claim 11 wherein the first cross member is electrically connected in common with the second cross member.

13. A semiconductor device comprising:

a substrate having a surface;

a housing coupled to the substrate, wherein the housing includes a major surface above the surface of the substrate, first and second edge surfaces orthogonal to the major surface and the surface of the substrate, and a third edge surface orthogonal to the major surface and extending between the first and second edge surfaces;

a first connector that projects outward from the first edge surface of the housing;

a second connector that projects outward from the second edge surface of the housing;

electronic circuitry on the substrate and comprising a plurality of electrical components, wherein the circuitry has one or more first electrical devices coupled to the first connector, and one or more second electrical devices coupled to the second connector, wherein the first and second electrical devices are electrically coupled together within the housing, and wherein the housing encloses the first and second electrical devices;

a ground connector that projects outward from the third edge surface between the first and second connectors; and

an isolation structure having an elongated first cross member coupled to the housing, and spaced from and extending over the surface of the substrate between the first and second electrical devices, wherein a length of the first cross member is greater than a width of the first cross member, and an area of the first cross member is smaller than an area of the surface of the substrate, and wherein the isolation structure further includes a first leg coupled to the housing and extending transverse to the first cross member and to the surface of the substrate, wherein the first leg is directly connected to the ground connector, the first leg has a width dimension that is parallel to and smaller than a distance between the first and second edge surfaces, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first and second electrical devices during an operation of the circuitry.

14. The semiconductor device as recited in claim 13 , wherein the isolation structure is formed of electrically conductive material.

15. The semiconductor device as recited in claim 13 , wherein the first cross member is located on an exterior surface of the housing.

16. The semiconductor device as recited in claim 13 , wherein the first cross member is within the housing.

17. The semiconductor device as recited in claim 13 , wherein the isolation structure further comprises a second leg extending transverse to the surface of the substrate and attached to the first cross member.

18. A semiconductor device comprising:

a substrate having a surface;

a housing coupled to the substrate, wherein the housing includes a major surface above the surface of the substrate, and first and second edge surfaces orthogonal to the major surface and the surface of the substrate;

a first connector that projects outward from the first edge surface of the housing;

a second connector that projects outward from the second edge surface of the housing;

electronic circuitry on the substrate and comprising a plurality of electrical components, wherein the circuitry has one or more first electrical devices coupled to the first connector, and one or more second electrical devices coupled to the second connector, wherein the first and second electrical devices are electrically coupled together within the housing, and wherein the housing encloses the first and second electrical devices;

a ground connector that projects outward from the housing between the first and second connectors; and

an isolation structure having

a first cross member coupled to the housing, and spaced from and extending over the surface of the substrate between the first and second electrical devices,

a second cross member spaced from and extending over the surface of the substrate, and

a first leg coupled to the housing and extending transverse to the first cross member and to the surface of the substrate,

wherein the first leg is directly connected to the ground connector, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first and second electrical devices during an operation of the circuitry.

19. The semiconductor device as recited in claim 18 wherein the first cross member is electrically connected in common with the second cross member.

20. A system comprising:

a packaged semiconductor device that includes:

a substrate having a surface,

a first circuit on the substrate and comprising a plurality of electrical components, and

a second circuit on the substrate and comprising another plurality of electrical components;

a housing coupled to the substrate, wherein the housing includes a major surface above the surface of the substrate, and an edge surface orthogonal to the major surface and the surface of the substrate, and wherein the housing encloses the first and second circuits;

first and second connectors that project outward from the edge surface of the housing, wherein the first connector is coupled to the first circuit, the second connector is coupled to the second circuit, and the first and second connectors are physically separated from each other by a first distance across a portion of the edge surface;

a ground connector that projects outward from the edge surface of the housing between the first and second connectors; and

an isolation structure having an elongated first cross member coupled to the housing, and spaced from and extending over the surface of the substrate between the first circuit and the second circuit, wherein a length of the first cross member is greater than a width of the first cross member, and an area of the first cross member is smaller than an area of the surface of the substrate, and wherein the isolation structure further includes a first leg coupled to the housing and extending transverse to the first cross member and to the surface of the substrate, wherein the first leg is directly connected to the ground connector, the first leg has a width dimension that is parallel to and smaller than the first distance between the first and second connectors, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

21. The system of claim 20 , wherein the isolation structure is coupled to at least one lead of the packaged semiconductor device.

22. The system of claim 20 , wherein the isolation structure is coupled to a conductive flange to which the first circuit and the second circuit are coupled.

23. A system comprising:

a packaged semiconductor device that includes:

a substrate having a surface,

a first circuit on the substrate and comprising a plurality of electrical components, and

a second circuit on the substrate and comprising another plurality of electrical components,

a housing coupled to the substrate, wherein the housing includes a major surface above the surface of the substrate, and an edge surface orthogonal to the major surface and the surface of the substrate, and wherein the housing encloses the first and second circuits,

first and second connectors that project outward from the housing, wherein the first connector is coupled to the first circuit, and the second connector is coupled to the second circuit,

a ground connector that projects outward from the edge surface of the housing between the first and second connectors, and

an isolation structure having a first cross member coupled to the housing, and spaced from and extending over the surface of the substrate between the first circuit and the second circuit, and a first leg coupled to the housing and extending transverse to the first cross member and to the surface of the substrate, wherein the first leg is directly connected to the ground connector, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit; and

a circuit board to which the packaged semiconductor device is coupled, wherein the isolation structure is coupled to the circuit board and extends over the packaged semiconductor device.

24. A method of fabricating a circuit with isolation between portions of the circuit, the method comprising:

forming a first circuit on a substrate of a semiconductor device;

forming a second circuit on the substrate adjacent to the first circuit;

coupling a housing to the substrate, wherein the housing includes a major surface above the surface of the substrate, and an edge surface orthogonal to the major surface and the surface of the substrate, and wherein the housing encloses the first and second circuits;

coupling a first connector to the first circuit, wherein the first connector projects outward from the edge surface of the housing;

coupling a second connector to the second circuit, wherein the second connector projects outward from the edge surface of the housing, and the first and second connectors are physically separated from each other by a first distance across a portion of the edge surface;

coupling a ground connector to the housing, wherein the ground connector projects outward from the housing between the first and second connectors; and

coupling an isolation structure of electrically conductive material to the housing between the first circuit and the second circuit, the isolation structure having at least an elongated first cross member coupled to the housing, and spaced from and extending over the surface of the substrate between the first circuit and the second circuit, wherein a length of the first cross member is greater than a width of the first cross member, and an area of the first cross member is smaller than an area of the surface of the substrate, and wherein the isolation structure further includes a first leg coupled to the housing and extending transverse to the first cross member and to the surface of the substrate, wherein the first leg is directly connected to the ground connector, the first leg has a width dimension that is parallel to and smaller than the first distance between the first and second connectors, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

25. The method as recited in claim 24 wherein the cross member and the first leg are formed on at least one surface of the housing.

26. The method as recited in claim 24 wherein coupling an isolation structure further comprises extending a second leg transverse to a plane of the substrate, wherein the second leg is electrically connected to the cross member.

Assignments (28)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2014
From: WATTS, MICHAEL E.; KUO, SHUN MEEN; SZYMANOWSKI, MARGARET A.
To: FREESCALE SEMICONDUCTOR, INC.
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