Granted Patent B2

US 9,325,549 · App. 14/287,574 · Granted Apr 26, 2016

Abstract

Claims (96)

1. A converter unit for an M-order digital modulation, the convertor unit being arranged to map L input binary sequences of N bits onto M complex values, the M complex values being transmitted through a communication channel, M=2 N , L and N being positive integers, the converter unit comprising:

an input for receiving a respective input binary sequence, the converter unit being arranged to individually convert each N bits of the input binary sequence into a real number to obtain a sequence of real numbers with N real numbers, corresponding to the input binary sequence, the converter unit being arranged to execute complex arithmetic operations on the sequence of real numbers, to compute a respective complex value of the M complex values, the respective complex value corresponding to said respective input binary sequence, and to map the computed M complex values onto a single constellation diagram;

wherein the M-order digital modulation is an eight-order Phase Shift Keying, the respective input binary sequence of N bits has three bits and the sequence with N real numbers has three real numbers; and

wherein the real number of the sequence is equivalent to 1 when the corresponding bit of the input binary sequence is equivalent to a binary 0, wherein the real number is equivalent to −1 when the corresponding bit of the respective input binary sequence is equivalent to a binary 1, and wherein the converter unit is arranged to:

compute a first sum of a first real number multiplied by the imaginary number j, with a second real number,

compute a difference of a third real number and the imaginary number j,

compute a real part of a first multiplication of the first sum with said difference,

compute a second sum (z 4 ) of a first number equivalent to

2

2

with a second multiplication of a second number equivalent to

-

2

-

1

+

j

4

with the modulus of said real part, and

compute the complex value corresponding to the input binary sequence as a third multiplication of said first sum with said second sum.

2. A converter unit according to claim 1 , further comprising a processor arranged to convert each one of the N bits of the respective input binary sequence into the real number, and a vector signal processor arranged to execute the complex arithmetic operations on the N real numbers.

3. A converter unit as claimed in claim 2 , wherein the vector signal processor has a predetermined clock frequency, and wherein the vector signal processor is further arranged to execute in parallel at least two complex arithmetic operations in a same clock cycle.

4. A converter unit as claimed in claim 1 , wherein the M-order digital modulation is an M-order Phase Shift Keying.

5. A converter unit as claimed in claim 1 , further arranged to compute a further complex value as a fourth multiplication of the third multiplication by

ⅇ

j

⁢

⁢

k

⁢

π

8

,

wherein k is an integer positive or negative, to obtain the further complex value rotated by

k

⁢

π

8

with respect to the respective complex value.

6. A converter unit as claimed in claim 1 comprising a memory arranged to store the first real number and the second real number in a first line array of the memory with a first predetermined precision to compute the first sum, and for storing the third real number and the imaginary number j in a second line array of the memory with the same first predetermined accuracy to compute the difference, wherein the first predetermined accuracy and an accuracy of the arithmetic operations executed by the converter unit determine the accuracy of the mapped respective complex value.

7. An integrated circuit comprising the converter unit as claimed in claim 1 .

8. A transmitter for transmitting data through a communications channel, comprising

a modulator for modulating a modulated signal by determining a complex value out of a discrete set of M preset complex values, M positive integer, according to a predetermined mapping of a M-order digital modulation, the modulator comprising the converter unit as claimed in claim 1 , and

a transmitter antenna electrically coupled the modulator for transmitting the modulated signal over a communication channel, the modulated signal comprising a modulated parameter having a complex value out of the discrete set of M preset complex values.

9. A digital communications system comprising the converter unit as claimed in claim 1 , and further a receiver, a receiver antenna and a demodulator.

10. A digital communications system as claimed in claim 9 , arranged to perform orthogonal frequency division multiple access, OFDMA, or code division multiple access, CDMA, or phase shift keying, PSK, modulation.

11. A method of mapping L input binary sequences of N bits onto M complex values, the M complex values being transmitted through a communication channel, M=2 N , being L and N positive integers, the method comprising:

receiving a respective one of the L input binary sequences;

converting individually each N bits of the input binary sequence into a real number to obtain a sequence of real numbers with N real numbers corresponding to the respective input binary sequence;

executing complex arithmetic operations on the sequence of real numbers to compute a respective complex value of the M complex values, the respective complex value corresponding to said respective input binary sequence, wherein the executing further comprises:

multiplying a first real number by the imaginary number j to obtain a first intermediate product,

summing the first intermediate product with a second real number to obtain a first sum,

subtracting a third real number and the imaginary number j to obtain a difference,

multiplying the first sum with said difference to obtain a second intermediate product,

compute a real part of said second intermediate product to obtain a real part,

multiplying a second number equivalent to

-

2

-

1

+

j

4

 with the modulus of said real part to obtain a third intermediate product,

summing a first number equivalent to

2

2

 with said third intermediate product to obtain a second sum, and

multiplying the first sum with second sum to obtain the respective complex value corresponding to the respective input binary sequence; and

mapping the computed M complex values onto a single constellation diagram, wherein the M-order digital modulation is an 8-PSK modulation, the respective input binary sequence of N bits has three bits, the sequence of real numbers has three real numbers, and wherein the converting converts the bit of the input binary sequence equivalent to a binary 0 onto a real number of the sequence equivalent to −1, and the bit of the input binary sequence equivalent to a binary 1 onto a real number of the sequence equivalent to 1.

12. A method as claimed in claim 11 wherein the executing complex arithmetic operations is performed in parallel for at least two complex arithmetic operations.

13. A non-transitory computer readable medium embodying a computer program comprising instructions for causing a processor unit to perform a method of mapping L input binary sequences of N bits onto M complex values, the M complex values being transmitted through a communication channel, M=2 N , being L and N positive integers, the method comprising:

receiving a respective one of the L input binary sequences;

converting individually each N bits of the input binary sequence into a real number to obtain a sequence of real numbers with N real numbers corresponding to the respective input binary sequence;

executing complex arithmetic operations on the sequence of real numbers to compute a respective complex value of the M complex values, the respective complex value corresponding to said respective input binary sequence, wherein the executing further comprises:

multiplying a first real number by the imaginary number j to obtain a first intermediate product;

summing the first intermediate product with a second real number to obtain a first sum;

subtracting a third real number and the imaginary number j to obtain a difference;

multiplying the first sum with said difference to obtain a second intermediate product;

compute a real part of said second intermediate product to obtain a real part;

multiplying a second number equivalent to

-

2

-

1

+

j

4

 with the modulus of said real part to obtain a third intermediate product;

summing a first number equivalent to

2

2

 with said third intermediate product to obtain a second sum; and

multiplying the first sum with second sum to obtain the respective complex value corresponding to the respective input binary sequence; and

mapping the computed M complex values onto a single constellation diagram, wherein the M-order digital modulation is an 8-PSK modulation, the respective input binary sequence of N bits has three bits, the sequence of real numbers has three real numbers, and wherein the converting converts the bit of the input binary sequence equivalent to a binary 0 onto a real number of the sequence equivalent to −1, and the bit of the input binary sequence equivalent to a binary 1 onto a real number of the sequence equivalent to 1.

14. The non-transitory computer readable medium of claim 13 , wherein the executing complex arithmetic operations is performed in parallel for at least two complex arithmetic operations.

Assignments (26)