IP Library Granted Patent US 9,515,006
Granted Patent B2
US 9,515,006 · App. 14/303,128 · Granted Dec 6, 2016

3D device packaging using through-substrate posts

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Quick Facts
Patent No.
US 9,515,006
App. No.
14/303,128
Granted
Dec 6, 2016
Kind
B2
Abstract

A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. The second die includes a third surface and a set of metal posts. The first die and the second die are stacked such that the third surface of the second die faces the second surface of the first die, and each metal post extends through a corresponding through-hole to a point beyond the first surface of the first die, electrically coupling the first die and the second die.

Claims (46)

1. A device package comprising:

a first semiconductor die comprising:

a first set of through-holes in a first arrangement, each through-hole of the first set of through-holes extending between a first surface of the first semiconductor die and a second surface of the first semiconductor die; and

a second semiconductor die comprising:

a first set of metal posts disposed at a third surface of the second semiconductor die in a second arrangement corresponding to the first arrangement, the third surface facing the second surface, and each metal post of the first set of metal posts extending through a corresponding through-hole of the first set of through-holes to a point beyond the first surface of the first semiconductor die.

2. The device package of claim 1 , wherein the metal posts of the first set of metal posts comprise at least one of pillars and stud bumps.

3. The device package of claim 1 , wherein

the second semiconductor die further comprises a set of pads at the third surface; and

the through-holes of the first set of through-holes further extend through the set of pads.

4. The device package of claim 1 , further comprising:

a third semiconductor die comprising:

a fourth surface; and

a set of holes, such that the fourth surface faces the third surface of the second semiconductor die and the first surface of the first semiconductor die, and such that each metal post of a second set of metal posts of the third semiconductor die extends into the set of holes of the third semiconductor die.

5. The device package of claim 4 , wherein the metal posts of the second set of metal posts comprise at least one of pillars and stud bumps.

6. The device package of claim 1 , further comprising:

a third semiconductor die comprising:

a fourth surface; and

a set of holes, such that the fourth surface faces the third surface of the second semiconductor die and the first surface of the first semiconductor die and the first set of metal posts extend through the set of holes.

7. The device package of claim 6 , wherein the metal posts of the first set of metal posts comprise at least one of pillars and stud bumps.

8. The device package of claim 6 , wherein:

the set of holes comprises a set of access holes extending from the fourth surface of the third semiconductor die to a set of pads at a metal layer of the third semiconductor die; and

each metal post of the first set of metal posts is electrically coupled to a corresponding pad of the set of pads.

9. The device package of claim 6 , wherein the set of holes comprises a second set of through-holes extending through the third semiconductor die.

10. A method comprising:

stacking a first semiconductor die and a second semiconductor die, such that a first surface of the first semiconductor die faces a second surface of the second semiconductor die and such that each metal post of a first set of metal posts of the first semiconductor die extends from the first surface of the first semiconductor die beyond a third surface of the second semiconductor die opposite the second surface via a corresponding through-hole of a first set of through-holes of the second semiconductor die; and

bonding the first semiconductor die and the second semiconductor die such that the metal posts of the first set of metal posts are electrically coupled to the second semiconductor die.

11. The method of claim 10 , wherein the metal posts of the first set of metal posts comprise at least one of pillars and stud bumps.

12. The method of claim 10 , wherein the through-holes of the first set of through-holes further extend through a set of pads at the third surface of the second semiconductor die.

13. The method of claim 10 , further comprising:

stacking a third semiconductor die comprising a fourth surface and a set of holes, such that the fourth surface faces the third surface of the second semiconductor die and the first surface of the first semiconductor die, and such that each metal post of a second set of metal posts of the third semiconductor die extends into the set of holes of the third semiconductor die; and

bonding the second semiconductor die and the third semiconductor die such that the metal posts of the second set of metal posts are electrically coupled to the third semiconductor die.

14. The method of claim 10 , further comprising:

stacking a third semiconductor die comprising a fourth surface and a set of holes, such that the fourth surface faces the third surface of the second semiconductor die and the first surface of the first semiconductor die and the first set of metal posts extend through the set of holes; and

bonding the first semiconductor die and the third semiconductor die such that the metal posts of the first set of metal posts are electrically coupled to the third semiconductor die.

15. The method of claim 14 , wherein:

the set of holes comprises a set of access holes extending from the fourth surface of the third semiconductor die to a set of pads at a metal layer of the third semiconductor die; and

each metal post of the first set of metal posts is electrically coupled to a corresponding pad of the set of pads.

16. The method of claim 14 , wherein the set of holes comprises a second set of through-holes extending through the third semiconductor die.

17. A method comprising:

forming a set of through-holes in a first arrangement at a first semiconductor die, each through-hole of the set of through-holes extending through the first semiconductor die from a first surface of the first semiconductor die to a second surface of the first semiconductor die; and

bonding the first semiconductor die and a second semiconductor die, the second semiconductor die comprising a set of metal posts disposed at a surface of the second semiconductor die in a second arrangement corresponding to the first arrangement, the set of metal posts extending through the first semiconductor die beyond the second surface via the set of through-holes.

18. The method of claim 17 , wherein each through-hole of the set of through-holes comprises at least one substantially flat wall that provides a gap between the through-hole and the corresponding metal post extending through the through-hole.

19. The method of claim 17 , further comprising:

forming a set of metal annular ring structures within the first semiconductor die, each annular ring structure forming a boundary of a corresponding through-hole of the set of through-holes.

20. The method of claim 17 , further comprising:

forming a dielectric barrier in each through-hole of the set of through-holes between one or more layers of the first semiconductor die and the corresponding metal post of the set of metal posts.

Assignments (28)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2014
From: REBER, DOUGLAS M.; SHROFF, MEHUL D.; TRAVIS, EDWARD O.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033094/0623 →