SYSTEM ON A CHIP, CONTROLLER AND METHOD FOR SECURING DATA
A system on a chip for securing data is described. The system on a chip comprises: a controller arranged to: partition a data block into a plurality of segments; and determine and extract a subset of the plurality of segments to be compressed. A compressor logic circuit is arranged to receive and compress the subset of the plurality of segments. The controller is arranged to retrieve the compressed subset of the plurality of segments from the compressor logic circuit and attach the compressed subset of the plurality of segments to a remainder of the partitioned data block for transmission.
1 . A system on a chip for securing data, the system on a chip comprising:
a controller arranged to:
partition a data block into a plurality of segments; and
determine and extract a subset of the plurality of segments to be compressed; and
a compressor logic circuit arranged to:
receive and compress the subset of the plurality of segments;
wherein the controller is arranged to retrieve the compressed subset of the plurality of segments from the compressor logic circuit and attach the compressed subset of the plurality of segments to a remainder of the partitioned data block for transmission.
2 . The system on a chip of claim 1 , wherein the controller is arranged to use a random striping seed in order to randomly determine a number of the partitioned data segments that are to be compressed.
3 . The system on a chip of claim 1 , wherein the controller is further arranged to detect a security breach and in response thereto implement a security breach measure.
4 . The system on a chip of claim 3 , wherein in response to the controller detecting a security breach, the security breach measure comprises the controller being further arranged to delete at least one of: knowledge of a random striping seed, a location of a random striping seed.
5 . The system on a chip of claim 2 , wherein the controller is arranged to scramble a location of the compressed partitioned data segments in the data block relative to their positions in an original data block.
6 . The system on a chip of claim 5 , wherein the random striping seed is variable to change an amount of striping dependent on an operational bandwidth of the system.
7 . The system on a chip of claim 1 , further comprising an encryption logic circuit arranged to receive and encrypt the transmitted data block with the attached compressed subset of the plurality of segments.
8 . The system on a chip of claim 1 , wherein the controller is arranged to attach the compressed subset of the plurality of segments to at least one of: a beginning of the partitioned data block for transmission, an end of the partitioned data block for transmission, a random location in the partitioned data block for transmission identified by an offset wherein the offset is stored in a known location in the code to facilitate decompression.
9 . The system on a chip of claim 1 , wherein the controller is operably coupled via a control fabric to at least one of: at least one core, at least one peripheral, at least one memory, a key generator 209 , a secure memory.
10 . The system on a chip of claim 1 , wherein the data block is partitioned according to a key.
11 . The system on a chip of claim 10 , wherein the controller is arranged to partition located data block based on a size of the key.
12 . The system on a chip of claim 10 , wherein the key is located within the data block transmitted to an encryption logic circuit.
13 . The system on a chip of claim 10 , wherein the key is deleted upon a security breach being detected, thereby preventing decompression of the partitioned data block.
14 . The system on a chip of claim 10 , wherein the key is based on one of: a user defined key, a secure key, a key generated by a random key generator coupled to the controller.
15 . The system on a chip of claim 1 , wherein the random key generator is arranged to determine for each of the plurality of segments whether it will compress the segment once that segment is read.
16 . The system on a chip of claim 1 , wherein the controller is arranged to extract a subset of the plurality of segments to be compressed and aggregate a plurality of segments of the subset to form a further block of data comprising data that is identified to be compressed.
17 . The system on a chip of claim 1 , further comprising a data storage operably coupled to the controller such that the controller is arranged to perform at least one of a group of:
transmit the compressed subset of the plurality of segments attached to the partitioned data block to the data storage,
be programmed with information on a location of data contained within the data storage that is to be secured.
18 . A controller for securing data, the controller arranged to:
partition a data block into a plurality of segments; and
determine and extract a subset of the plurality of segments to be compressed; and
retrieve a compressed subset of the plurality of segments from a compressor logic circuit and attach the compressed subset of the plurality of segments to a remainder of the partitioned data block for transmission.
19 . A method of securing data, comprising:
partitioning a data block into a plurality of segments;
determining and extracting a subset of the plurality of segments to be compressed;
receiving and compressing the subset of the plurality of segments;
retrieving the compressed subset of the plurality of segments; and
attaching the compressed subset of the plurality of segments to a remainder of the partitioned data block for transmission.
20 . The method of securing data of claim 19 , further comprising:
detecting a security breach; and in response thereto
implementing a security breach measure.