TIN-BASED WIREBOND STRUCTURES
Tin-based wirebond structures and wirebonds formed thereon. In some embodiments, an electronic package includes a semiconductor die located over a substrate and a wire configured to couple a terminal of the semiconductor die to a bond pad on the substrate. A wire bond between the wire and the bond pad may include an amount of tin originated from a layer of tin alloy formed on the bond pad. In other embodiments, a wirebond structure may include a conductive layer and a layer of tin alloy located over a portion of the conductive layer. The layer of tin alloy may provide a wirebonding contact surface configured to receive a bond wire.
1 . An electronic package, comprising:
a semiconductor die located over a substrate; and
a wire configured to couple a terminal of the semiconductor die to a bond pad on the substrate, wherein a wire bond between the wire and the bond pad includes an amount of tin originated from a layer of tin alloy formed on the bond pad.
2 . The electronic package of claim 1 , wherein the layer of tin alloy includes at least 85% tin by weight.
3 . The electronic package of claim 1 , wherein the layer of tin alloy includes at least one element selected from the group consisting of: nickel, titanium, copper, silver, palladium, iron, cobalt, cadmium, zinc, manganese, gold, aluminum, and antimony.
4 . The electronic package of claim 1 , wherein the layer of tin alloy has a solidus temperature and a liquidus temperature above a wire bonding temperature.
5 . The electronic package of claim 1 , wherein the layer of tin alloy has a thickness of 1.5 μm or less.
6 . The electronic package of claim 5 , wherein the layer of tin alloy has a thickness between 0.8 and 1.2 μm.
7 . The electronic package of claim 1 , wherein the layer of tin alloy has a hardness of 8.0 HB or more at room temperature.
8 . The electronic package of claim 7 , wherein the layer of tin alloy has a hardness between 8.0 HB and 30 HB at room temperature.
9 . The electronic package of claim 1 , further comprising a layer of intermetallic compounds (IMC) between the conductive layer and the layer of tin alloy.
10 . The electronic package of claim 1 , further comprising a barrier layer between the conductive layer and the layer of tin alloy.
11 . The electronic package of claim 1 , wherein at least a portion of the layer of tin alloy remains over the bond pad at a location outside the area of the wirebond.
12 . The electronic package of claim 1 , wherein the bond pad includes copper.
13 . A wirebond structure, comprising:
a conductive layer; and
a layer of tin alloy located over a portion of the conductive layer, wherein the layer of tin alloy provides a wirebonding contact surface configured to receive a bond wire.
14 . The wirebond structure of claim 13 , wherein the layer of tin alloy includes at least 85% tin by weight.
15 . The wirebond structure of claim 13 , wherein the layer of tin alloy has a thickness of 1.5 μm or less.
16 . The wirebond structure of claim 13 , wherein the layer of tin alloy has a hardness between 8.0 HB and 30 HB at room temperature.
17 . The wirebond structure of claim 13 , wherein the conductive layer is characterized as copper.
18 . An electronic package, comprising:
a semiconductor die located over a substrate, the substrate including a wirebondable structure, the wirebondable structure including:
a dielectric layer;
a conductive layer located over a portion of the dielectric layer, wherein the conductive layer includes copper;
a layer of tin alloy located at least over a portion of the conductive layer; and
a wire configured to couple a terminal of the semiconductor die to a bond pad on the portion of the conductive layer, wherein a wire bond between the wire and the bond pad includes an amount of tin originated from the layer of tin alloy.
19 . The electronic package of claim 18 , wherein the layer of tin alloy includes at least one element selected from the group consisting of: nickel, titanium, copper, silver, palladium, iron, cobalt, cadmium, zinc, manganese, gold, aluminum, and antimony.
20 . The electronic package of claim 18 , wherein the layer of tin alloy has a hardness between 8.0 HB and 30 HB at room temperature.