IP Library Granted Patent US 9,548,280
Granted Patent B2
US 9,548,280 · App. 14/243,649 · Granted Jan 17, 2017

Solder pad for semiconductor device package

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,548,280
App. No.
14/243,649
Granted
Jan 17, 2017
Kind
B2
Abstract

A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices and methods providing improved solder ball pad structures in a device such as a semiconductor device package.

Claims (38)

1. A semiconductor device package, comprising:

a solder ball pad formed on a first dielectric layer, the solder ball pad having a central pad portion, a perimeter, and an edge about the perimeter, the central pad portion defining and encircling a solder ball mounting area situated inward from the edge about the perimeter, and a recessed portion within the central pad portion at an end of the solder ball pad; and

a second dielectric layer formed over the solder ball pad including the perimeter, edge and the central pad portion encircling the solder ball mounting area;

wherein

the perimeter of the solder ball pad comprises a plurality of outwardly extending protrusions extending about the perimeter up to the recessed portion, the protrusions configured to lock the solder ball pad including the edge and the central pad portion encircling the solder ball mounting area to the second dielectric layer to inhibit delamination of the second dielectric layer therefrom, including at least a first protrusion and a second protrusion adjacent to the first protrusion, the first protrusion and the second protrusion spaced apart at a distance to confine delamination of the second dielectric layer from the solder ball pad to an area between the first protrusion and the second protrusion, each of the protrusions having a first surface, a second surface and a distal end, wherein the distal ends of each of the protrusions are not interconnected to each other; and

the second dielectric layer completely covers the plurality of protrusions, the entire perimeter of the solder ball pad including the edge, and the central pad portion of the solder ball pad encircling the solder ball mounting area but not the solder ball mounting area.

2. The semiconductor device package of claim 1 , wherein the plurality of protrusions each have opposing sides, a distal end, and a protrusion length, and the protrusion length is effective to limit a delamination to one side and prior to the distal end.

3. The semiconductor device package of claim 1 , wherein the protrusion length is about 10-100 μm.

4. The semiconductor device package of claim 1 , wherein the solder ball pad has a thickness of about 2 μm to less than 10 μm, and the protrusion length is about 10-75 μm.

5. The semiconductor device package of claim 1 , wherein the solder ball pad has a thickness of about 10-20 μm, and the protrusion length is about 25-100 μm.

6. The semiconductor device package of claim 1 , wherein the solder ball pad further comprises one or more through-holes situated along the perimeter and extending through the solder ball pad to the first dielectric layer, and the one or more through-holes are filled with the second dielectric layer.

7. The semiconductor device package of claim 6 , wherein the through-holes have a diameter of about 10-80 μm.

8. The semiconductor device package of claim 6 , wherein the solder ball pad has a thickness of about 2 μm to less than 10 μm, and the diameter of the through-holes is about 10-60 μm.

9. The semiconductor device package of claim 6 , wherein the solder ball pad has a thickness of about 10-20 μm, and the diameter of the through-holes is about 20-80 μm.

10. A method of making a semiconductor device package, the method comprising:

forming a solder ball pad on a first dielectric layer, the solder ball pad having a central pad portion, a perimeter, and an edge about the perimeter, the central pad portion defining and encircling a solder ball mounting area situated inward from the edge about the perimeter, and a recessed portion within the central pad portion at an end of the solder ball pad; and

forming a second dielectric layer over the solder ball pad including the perimeter, edge and the central pad portion encircling the solder ball mounting area;

wherein

said forming the solder ball pad comprises forming a locking feature comprising one or more features configured to lock the solder ball pad including the edge and the central pad portion encircling the solder ball mounting area to the second dielectric layer to inhibit delamination of the second dielectric layer from the solder ball pad; the locking feature comprising a plurality of outwardly extending protrusions extending about the perimeter up to the recessed portion, the protrusions including at least a first protrusion and a second protrusion adjacent to the first protrusion; the first protrusion and the second protrusion spaced apart at a distance so as to confine delamination of the second dielectric layer from the solder ball pad to an area between the first protrusion and the second protrusion, each of the protrusions having a first surface, a second surface and a distal end, wherein the distal ends of each of the protrusions are not interconnected to each other; and

the second dielectric layer completely covers the plurality of protrusions, the entire perimeter of the solder ball pad including the edge, and the central pad portion of the solder ball pad encircling the solder ball mounting area but not the solder ball mounting area.

11. The method of claim 10 , wherein forming the locking feature further comprises forming through-holes extending through the solder ball pad to the first dielectric layer, and forming the second dielectric layer comprises filling the through-holes with the second dielectric layer.

12. The method of claim 11 , wherein the locking feature comprises a plurality of through-holes along the perimeter of the solder ball pad.

13. The method of claim 10 , further comprising:

forming a multi-layer circuit interconnect on a semiconductor die; and

forming the first dielectric layer over the multi-layer circuit interconnect.

14. A semiconductor device package, comprising:

a solder ball pad formed on a first dielectric layer, the solder ball pad having a central pad portion, a perimeter, and an edge about the perimeter, the central pad portion defining and encircling a solder ball mounting area situated inward from the edge about the perimeter, and a recessed portion within the central pad portion at an end of the solder ball pad; and

a second dielectric layer formed over the solder ball pad including the perimeter, edge and the central pad portion encircling the solder ball mounting area;

wherein

the perimeter of the solder ball pad comprises a plurality of through-holes extending through the solder ball pad to the first dielectric layer and a plurality of outwardly extending protrusions, the protrusions extending about the perimeter up to the recessed portion and configured to lock the solder ball pad including the edge and the central pad portion encircling the solder ball mounting area to the second dielectric layer to inhibit delamination of the second dielectric layer therefrom, including at least a first protrusion and a second protrusion adjacent to the first protrusion, the first protrusion and the second protrusion spaced apart at a distance to confine delamination of the second dielectric layer from the solder ball pad to an area between the first protrusion and the second protrusion, each of the protrusions having a first surface, a second surface and a distal end, wherein the distal ends of each of the protrusions are not interconnected to each other, and the plurality of through-holes situated on the central pad portion between the edge about the perimeter and the solder ball mounting area; and

the second dielectric layer completely covers the plurality of protrusions, the entire perimeter of the solder ball pad including the edge, and the central pad portion of the solder ball pad encircling the solder ball mounting area but not the solder ball mounting area, and fills the plurality of through-holes.

15. A method of making a semiconductor device package, the method comprising:

forming a solder ball pad on a first dielectric layer, the solder ball pad having a central pad portion, a perimeter, and an edge about the perimeter, the central pad portion defining and encircling a solder ball mounting area situated inward from the edge about the perimeter, and a recessed portion within the central pad portion at an end of the solder ball pad; and

forming a second dielectric layer over the solder ball pad including the perimeter, edge and the central pad portion encircling the solder ball mounting area;

wherein

said forming the solder ball pad comprises forming a locking feature comprising one or more features configured to lock the solder ball pad including the edge and the central pad portion encircling the solder ball mounting area to the second dielectric layer to inhibit delamination of the second dielectric layer from the solder ball pad;

the locking feature comprising a plurality of through-holes extending through the solder ball pad to the first dielectric layer and a plurality of outwardly extending protrusions, the protrusions extending about the perimeter up to the recessed portion and including at least a first protrusion and a second protrusion adjacent to the first protrusion; the first protrusion and the second protrusion spaced apart at a distance so as to confine delamination of the second dielectric layer from the solder ball pad to an area between the first protrusion and the second protrusion, each of the protrusions having a first surface, a second surface and a distal end, wherein the distal ends of each of the protrusions are not interconnected to each other protrusions; and

the second dielectric layer completely covers the plurality of protrusions, the entire perimeter of the solder ball pad including the edge, and the central pad portion of the solder ball pad encircling the solder ball mounting area but not the solder ball mounting area, and fills the through-holes of the locking feature.

Assignments (28)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2014
From: SARIHAN, VIJAY; GONG, ZHIWEI; HAYES, SCOTT M.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032586/0426 →