Test mode entry interlock
View Patent ↗An integrated circuit having normal and special operating modes includes a mode entry interlock ( 201 ) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal ( 204 ) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal ( 212 ) for receiving a disassociated software command to enter into the special operating mode, and mode control logic ( 210, 216 ) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.
1. An integrated circuit device, comprising:
a first terminal for receiving an externally supplied voltage to force the first terminal to a first logic state;
an input/output buffer coupled to the first terminal, comprising:
an output buffer connected to drive the first terminal to a second logic state in response to a command input provided to the output buffer, and
an input buffer connected to convey a detected logic state from the first terminal as a first input signal in response to the externally supplied voltage being received at the first terminal;
a second terminal circuit for receiving a special mode entry command that is independent from the externally supplied voltage and for generating a second input signal; and
an evaluation circuit for generating a special mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the second logic state.
2. The integrated circuit device of claim 1 , where the first terminal, input/output buffer, and second terminal circuit are used by the integrated circuit device during normal operating mode.
3. The integrated circuit device of claim 1 , where the output buffer comprises an NMOS transistor that is source-drain coupled between the first terminal and a predetermined reference voltage and that is gated by the command input.
4. The integrated circuit device of claim 3 , where the NMOS transistor is sized so that the output buffer is unable to drive the first terminal to the second logic state when then externally supplied voltage is supplied to the first terminal.
5. The integrated circuit device of claim 3 , where the NMOS transistor is sized to not overheat or suffer electrical over-stress.
6. The integrated circuit device of claim 1 , where the output buffer comprises an NPN transistor configured as an open collector output stage.
7. The integrated circuit device of claim 1 , where the evaluation circuit comprises a combinatorial logic structure for logically combining the first and second input signals to generate the special mode enable signal.
8. The integrated circuit device of claim 1 , where the evaluation circuit generates the special mode enable signal only when the detected logic state conflicts with the second logic state at the time the special mode entry command is received.
9. The integrated circuit device of claim 1 , where the output buffer and input buffer are configured to be conflicting buffers for the first terminal.
10. The integrated circuit device of claim 1 , where the evaluation circuit is configured to continually provide the command input to the output buffer to drive the first terminal to the second logic state in response to a software command.
11. A method of operation, comprising:
driving an input/output (I/O) pin of an integrated circuit to a first logic state while simultaneously forcing the I/O pin to a second, different logic state, thereby creating a conflict condition at the I/O pin;
receiving a test mode entry command at a terminal circuit of the integrated circuit; and
generating a test entry signal by accepting the test mode entry command only if the conflict condition at the I/O pin is detected within a specified detection window after receiving the test mode entry command.
12. The method of claim 11 , where driving the I/O pin comprises driving a first I/O pin of the integrated circuit that is used during normal operation to the first logic state with a first output buffer while simultaneously forcing the first I/O pin to a second, different logic state with an externally supplied voltage, thereby creating the conflict condition at the first I/O pin.
13. The method of claim 12 , further comprising driving a signal input line to test mode control logic with a second input buffer connected to receive the first I/O pin, thereby enabling the test mode control logic to detect the conflict condition at the first I/O pin.
14. The method of claim 13 , further comprising receiving a first message, instruction, or other software command from a user, microcontroller, or other test entity which causes the test mode control logic to drive the first I/O pin of the integrated circuit to the first logic state.
15. The method of claim 14 , where receiving the test mode entry command comprises receiving a second message, instruction, or other software command from a user, microcontroller, or other test entity.
16. The method of claim 11 , where receiving the test mode entry command comprises receiving a second message, instruction, or other software command from a user, microcontroller, or other test entity.
17. The method of claim 11 , where driving the I/O pin comprises connecting an overdrive voltage source to the I/O pin to force the I/O pin to the second, different logic state.
18. The method of claim 11 , where generating the test entry signal comprises logically combining first and second input signals into an enter test mode command, where the first input signal is generated in response to receiving the test mode entry command, and where the second input signal is generated in response to the I/O pin being forced to the second, different logic state.
19. The method of claim 11 , where driving the I/O pin comprises:
connecting an output buffer to drive the I/O pin to the first logic state while simultaneously forcing the I/O pin to a second, different logic state, thereby creating a conflict condition at the I/O pin; and
connecting an input buffer to buffer the I/O pin to convey a detected logic state from the I/O pin as a first input signal which is processed by test mode control logic to detect the conflict condition at the I/O pin.
20. A special mode entry interlock circuit for an integrated circuit device, comprising:
a plurality of input/output pads, comprising a first input/output pad for receiving an externally supplied voltage during a special operating mode;
an output buffer connected to drive the first input/output pad to a first logic state in response to a first logic state input provided to the output buffer;
a conflicting input buffer connected to buffer a detected logic state from the first input/output pad as a first input signal;
a communication port circuit for receiving a special mode entry command that is independent from the externally supplied voltage and for generating a second input signal; and
special mode control logic for logically combining the first and second input signals to generate a special mode enable signal only when the detected logic state conflicts with the first logic state,
where the plurality of input/output pads, output buffer, conflicting input buffer, and communication port are used by the integrated circuit device during normal operating mode.