Methods and structures for charge storage isolation in split-gate memory arrays
View Patent ↗Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.
1. A method for forming a memory structure, the method comprising:
forming a charge storage layer over a semiconductor substrate;
forming a first control gate layer over the charge storage layer;
patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate;
filling the opening with an insulating material;
forming a second control gate layer over the patterned first control gate layer and the insulating material, wherein the second control gate layer is in physical contact with the patterned first control gate layer;
patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein:
the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and
the insulating material is between the first and second control gate electrodes,
forming a first select gate electrode adjacent a sidewall of the first control gate electrode and a second select gate electrode adjacent a sidewall of the second control gate electrode, wherein the insulating material is between the first and second select gate electrodes.
2. The method of claim 1 , further comprising:
after the filling the opening with the insulating material and prior to the forming the second control gate layer, recessing the insulating material with the opening wherein a top surface of the insulting material is between a top surface of the charge storage layer and a top surface of the patterned first control gate layer.
3. The method of claim 1 , wherein the charge storage layer comprises nanocrystals surrounded by a second insulating material.
4. The method of claim 1 , further comprising:
forming a first isolation layer along the sidewall of the first control gate electrode and a second isolation layer along the sidewall of the second control gate electrode.
5. The method of claim 4 , wherein the forming the first and second select gate electrodes comprises:
forming a select gate layer between the first and second isolation layers;
planarizing the select gate layer; and
patterning the select gate layer to form the first and second select gate electrodes, wherein the first isolation layer is between the first control gate electrode and the first select gate electrode and the second isolation layer is between the second control gate electrode and the second select gate electrode.
6. The method of claim 4 , wherein the forming the first and second select gate electrodes comprises:
forming a select gate layer between the first and second isolation layers; and
performing an anisotropic etch of the select gate layer to form the first and second select gate electrodes, wherein the first isolation layer is between the first control gate electrode and the first select gate electrode and the second isolation layer is between the second control gate electrode and the second select gate electrode.
7. The method of claim 1 , wherein the patterning the second control gate layer to form the first control gate electrode and the second control gate electrode is performed such that a first portion of the charge storage layer remains between the first control gate electrode and the substrate and a second portion of the charge storage layer remains between the second control gate electrode and the substrate, wherein the insulating material is between the first and second portions of the charge storage layer.
8. The method of claim 1 , further comprising:
forming a sidewall spacer adjacent a second sidewall of each of the first and second control gate electrodes and adjacent each of the first and second select gate electrodes.
9. The method of claim 1 , wherein the opening is formed such that it runs a length of a bit line of the memory structure.
10. The method of claim 1 , further comprising:
forming source/drain regions in the substrate between the select gate electrodes and adjacent the second sidewalls of the first and second control gate electrodes, wherein the opening extends further into the substrate than the source/drain regions.
11. The method of claim 1 , wherein, after the patterning the second control gate layer, the second control gate layer is continuous across the first and second control gate electrodes.
12. A method for forming a memory structure, the method comprising:
forming a charge storage layer comprising nanocrystals over a semiconductor substrate;
forming a first control gate layer over the charge storage layer;
patterning the first control gate layer to form a trench in the first control gate layer and the charge storage layer, wherein the trench extends into the substrate and extends along a length of a bit line of the memory structure;
filling the trench with an insulating material;
forming a second control gate layer directly on the patterned first control gate layer and over the insulating material;
patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, the trench located between the first and second gate electrodes, wherein:
each of the first and second control gate electrodes comprises a separate portion of the first control gate layer, and
the second control gate layer is continuous between the first and second control gate electrodes; and
forming a first select gate electrode adjacent a sidewall of the first control gate electrode and a second select gate electrode adjacent a sidewall of the second control gate electrode, wherein the insulating material is between the first and second select gate electrodes.
13. The method of claim 12 , further comprising:
after the filling the trench with the insulating material and prior to the forming the second control gate layer, recessing the insulating material with the trench wherein a top surface of the insulting material is between a top surface of the charge storage layer and a top surface of the patterned first control gate layer.
14. The method of claim 12 , further comprising:
forming a first isolation layer along the sidewall of the first control gate electrode and a second isolation layer along the sidewall of the second control gate electrode.
15. The method of claim 14 , wherein the forming the first and second select gate electrodes comprises:
forming a select gate layer between the first and second isolation layers;
planarizing the select gate layer; and
patterning the select gate layer to form the first and second select gate electrodes, wherein the first isolation layer is between the first control gate electrode and the first select gate electrode and the second isolation layer is between the second control gate electrode and the second select gate electrode.
16. The method of claim 14 , wherein the forming the first and second select gate electrodes comprises:
forming a select gate layer between the first and second isolation layers; and
performing an anisotropic etch of the select gate layer to form the first and second select gate electrodes, wherein the first isolation layer is between the first control gate electrode and the first select gate electrode and the second isolation layer is between the second control gate electrode and the second select gate electrode.
17. The method of claim 12 , wherein the patterning the second control gate layer to form the first control gate electrode and the second control gate electrode is performed such that a first portion of the charge storage layer remains between the first control gate electrode and the substrate and a second portion of the charge storage layer remains between the second control gate electrode and the substrate, wherein the insulating material is between the first and second portions of the charge storage layer.
18. The method of claim 12 , further comprising:
forming source/drain regions in the substrate between the select gate electrodes, and adjacent each of the first sidewall spacers, wherein the trench extends further into the substrate than the source/drain regions.