Granted Patent B1

US 9,094,908 · App. 14/258,394 · Granted Jul 28, 2015

Abstract

Claims (36)

1. A controller device for a data interface between sub-systems in a chain of at least two sub-systems in a mobile communication base station system, the sub-systems comprising at least one second sub-system and at least one first sub-system for controlling the second sub-system, at least one first sub-system being a synchronization master controlling a time synchronization of the sub-systems, the controller device comprising:

a clock input for receiving a reference clock;

a sync input for receiving an external synchronization signal;

a tracking clock circuit connected to the clock input and the sync input, for generating a transmit clock based on the reference clock signal and the synchronization signal, the tracking clock circuit comprising:

a controllable phase locked loop, (PLL), for generating the transmit clock, the PLL comprising a PLL output for outputting the transmit clock, a first phase input coupled to the reference clock and a second phase input coupled to the PLL output via a negative feedback loop; and

a frequency and phase tracking loop coupling the sync input and the second phase input to a control input of the controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase error between the external synchronization signal and the feedback signal; and

a transmitter for transmitting binary data from the first sub-system to the second subsystem, the binary data having a bit duration controlled by a clock cycle of the transmit clock, and the transmitter being connected with a clock input to the PLL output for clocking the transmitter with the transmit clock.

2. A device as claimed in claim 1 , wherein:

the negative feedback loop comprises a divider arranged to divide the frequency of the transmit clock and to output a divided transmit clock, the divider having a divider input coupled to the PLL output for receiving the transmit clock and having a diver output connected to the second phase input for providing to the second phase input the divided transmit clock; and

the phase detector is connected to a node between the divider and the second phase input;

and the phase control circuit is connected to a node between the PLL output and the divider input.

3. A device as claimed in claim 1 , wherein the PLL is a multiple-phase PLL having multiple PLL sub-outputs providing different phases of the transmit clock, and the phase control signal is connected to the PLL for selecting a PLL sub-output depending on the phase error detected by the phase detector.

4. A device as claimed in claim 1 , wherein the phase control circuit pulse width modulates the feedback signal and the PLL performs low-pass filtering of the feedback signal.

5. A device as claimed in claim 1 wherein the phase control circuit comprises a first integrator for integrating the phase error detected by the phase detector to obtain a value proportional to a frequency offset between the transmit clock and the reference clock.

6. A device as claimed in claim 1 , wherein the tracking clock circuit comprises a first pre-divider between the second phase input and the phase detector, the first pre-divider being arranged for dividing the frequency of the feedback signal by a first division factor.

7. A device as claimed in claim 1 , wherein the tracking clock circuit comprises a second pre-divider coupled between the sync input and the phase detector, the second pre-divider being arranged for dividing the frequency of the external synchronization signal by a second division factor.

8. A device as claimed in claim 1 , wherein the sync input is arranged for receiving a global position system (GPS) clock signal.

9. A device as claimed in claim 1 , wherein the sync input is arranged for receiving an Ethernet signal.

10. A device as claimed in claim 1 , wherein the data interface is compliant or compatible with the common public radio interface specification version 1.4, 2.1, 3.0, 4.0, 4.1, 4.2, 5.0 or 6.0.

11. A baseband subsystem for a base station in a mobile communication system, comprising a device according to claim 1 and in which the baseband subsystem constitutes the first subsystem and is a synchronization master.

12. A device as claimed in claim 4 , wherein the PLL comprises a multiplexer, nux, and phase control circuit comprises a mux control coupled to the output of the first integrator or the second integrator.

13. A device as claimed in claim 5 , wherein the integrator is a configurable integrator having a configuration input for adjusting an integrator gain to accommodate different transmit clock frequencies.

14. A device as claimed in claim 5 , wherein the phase control circuit comprises a second integrator for converting the frequency offset into a change in phase to be applied to the transmit clock.

15. A device as claimed in claim 6 , wherein the first division factor corresponds to a ratio of the frequency of the reference clock and the frequency of the external synchronization signal.

16. A device as claimed in claim 6 , wherein a ratio of the first division factor and the second division factor corresponds to a ratio of the frequency of the reference clock and the frequency of the external synchronization signal.

17. A device as claimed in claim 9 , wherein the sync input comprises an Ethernet controller for deriving a frame synchronization signal from the Ethernet signal.

18. A mobile communications base station system, comprising at least one chain of at least two sub-systems, the sub-systems comprising at least one second sub-system and at least one first sub-system for controlling the second sub-system, at least one first sub-systems being a synchronization master controlling a time synchronization of the sub-systems, wherein the first subsystem is a baseband subsystem as claimed in claim 11 , and the second subsystem is a radio frequency subsystem.

19. A method for controlling a base station system comprising at least one chain of at least two sub-systems, the sub-systems comprising at least one second sub-system and at least one first sub-system for controlling the second sub-system, at least one first sub-systems being a synchronization master controlling a time synchronization of the sub-systems, the method comprising:

receiving a reference clock at a clock input;

receiving an external synchronization signal at a sync input;

generating a transmit clock from the reference clock signal and the synchronization signal, said generating comprising:

a controllable phase locked loop, (PLL) receiving the reference clock at a first phase input, and generating the transmit clock, the PLL outputting the transmit clock at a PLL output and receiving at a second phase input a feedback signal from a negative feedback loop between the PLL output and the second phase input;

a phase detector, coupled to the sync input and the second phase input, detecting a phase error between the external synchronization signal and a feedback signal inputted at the second phase input; and

a phase control circuit generating a phase control signal based on the phase error, and coupling the phase control signal to a control input of the controllable PLL thereby modulating a frequency of the transmit clock; and

transmitting by a transmitter binary data from the first sub-system to the second subsystem, the binary data having a bit duration controlled by a clock cycle of the transmit clock, and clocking the transmitter with the transmit clock.

20. A non-transitory computer program product comprising instructions for causing a processor system to perform the method according to claim 19 .

Assignments (8)