Granted Patent B2

US 9,318,158 · App. 14/287,463 · Granted Apr 19, 2016

Abstract

Claims (37)

1. A memory cell comprising:

a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node;

a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail;

a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and a third power rail;

a column decode and control circuit configured to apply a same voltage to the first and second power rails during a write operation while the internal node is at a different voltage than the same voltage;

a second transistor coupled between the first current electrode of the first transistor and the first bitline, the second transistor having a first current electrode coupled to the first bitline, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode coupled to the read wordline;

a third transistor having a first current electrode coupled to a second bitline, a control electrode coupled to a write wordline, and a second current electrode coupled to the internal node, wherein the first bitline and the second bitline are a same bitline.

2. The memory cell of claim 1 , wherein when the first bi-directional resistive element has a higher resistance than the second bi-directional resistive element, the memory cell stores a first logic state, and when the first bi-directional resistive element has a lower resistance than the second bi-directional resistive element, the memory cell stores a second logic state.

3. The memory cell of claim 1 , wherein, during a read operation, the first transistor draws a current from the first bitline based on a difference in resistance between the first and second bi-directional resistive elements.

4. The memory cell of claim 1 , wherein, during the write operation, the first and second bi-directional resistive elements are written simultaneously due to the first and second bi-directional resistive elements being effectively coupled in parallel by the same voltage being set at the first and second power rails.

5. The memory cell of claim 4 , wherein during the write operation, the third transistor couples the second bitline to the internal node, wherein when the different voltage at the internal node is at least a predetermined amount greater than the same voltage of the first and second power rails, a first logic state is written to the memory cell and when the different voltage at the internal node is at least the predetermined amount less than the same voltage of the first and second power rails, a second logic state is written to the memory cell.

6. The memory cell of claim 1 , wherein one of a group consisting of the second and third power rails are a same power rail, and the first and third power rails are a same power rail.

7. A method of operating a memory cell having a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, and a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, the method comprising:

during a read operation:

coupling the first and second bi-directional resistive elements in series between the first power rail and the second power rail, and

coupling the internal node to a control electrode of a pull-down transistor configured to draw current from a first bitline based on a difference in resistance between the first and second bi-directional resistive elements; and

during a write operation:

coupling the internal node to a second bitline, wherein the first bitline and the second bitline are a same bitline,

setting the first power rail to a first voltage different from a voltage of the second bitline, and

setting the second power rail to the first voltage.

8. The method of claim 7 , wherein, during the write operation, a polarity between the voltage of the second bitline and the first power rail is a same polarity as a polarity between the voltage of the second bitline and the second power rail.

9. The method of claim 7 , wherein during the write operation, when a voltage at the internal node is at least a predetermined amount greater than the first voltage, the method comprises writing a first logic state to the memory cell, and when the voltage at the internal node is at least a predetermined amount lower than the first voltage, the method comprises writing a second logic state to the memory cell.

10. The method of claim 7 , further comprising, during the read operation, sensing the first bitline to determine a logic state stored in the memory cell.

11. A memory comprising:

an array of memory cells, wherein each memory cell comprises:

a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node;

a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail;

a first transistor having a control electrode coupled to the internal node, a first current electrode, and a second current electrode coupled to a third power rail;

a second transistor having a first current electrode coupled to a first bitline, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode coupled to a read wordline; and

a third transistor having a first current electrode coupled to a second bitline, a control electrode coupled to a write wordline, and a second current electrode coupled to the internal node, wherein, in each memory cell of the memory array of memory cells, the first bitline and the second bitline are a same bitline, and one of a group consisting of the second and third power rails are a same power rail, and the first and third power rails are a same power rail;

column decode circuitry coupled to the first and second power rails, and to the first bitline of each memory cell of the array of memory cells; and

row decode circuitry coupled to the read and write wordlines of each memory cell of the array of memory cells,

wherein during a write operation, the column decode circuitry is configured to apply a same voltage to the first and second power rails and a different voltage to the first and second bit lines, and for each memory cell coupled to an activated write wordline, the third transistor couples the second bitline to the internal node,

wherein when the different voltage at the internal node is at least a predetermined amount greater than the same voltage of the first and second power rails, a first resistance state is written simultaneously to the first and second bi-directional elements of the memory cell, and

when the different voltage at the internal node is at least the predetermined amount less than the same voltage of the first and second power rails, a second resistance state is written simultaneously to the first and second bi-directional elements of the memory cell.

12. The memory of claim 11 , wherein, during a read operation, for each memory cell coupled to an activated read wordline, the first transistor is configured to draw current from the first bitline based on a difference in resistance between the first and second bi-directional resistive elements, wherein for each memory cell of the array of memory of cells, when the first bi-directional resistive element has a higher resistance than the second bi-directional resistive element, the memory cell stores a first logic state, and when the first bi-directional resistive element has a lower resistance than the second bi-directional resistive element, the memory cell stores a second logic state.

13. The memory of claim 11 , wherein at least one of the first power rail and the second power rail is shared between adjacent columns of the array of memory cells.

Assignments (16)