IP Library Granted Patent US 9,641,140
Granted Patent B2
US 9,641,140 · App. 14/317,864 · Granted May 2, 2017

Method and apparatus for a multi-harmonic matching network

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,641,140
App. No.
14/317,864
Granted
May 2, 2017
Kind
B2
Abstract

A matching network and method for matching a source impedance to a load impedance is provided. A bias feed microstrip structure is coupled to a direct current (DC) voltage source and has a bias feed microstrip electrical length less than one fifth of a fundamental wavelength of a fundamental frequency component of an input signal. A harmonic impedance transformation network can be configured to compensate for parasitic reactances of a precursor element. A tuned impedance element presents a short circuit impedance at the second harmonic impedance transformation network terminal for harmonic frequency components and presents a higher impedance for the fundamental frequency component. A fundamental impedance transformation network is configured to match a fundamental impedance transformation network input impedance for the fundamental frequency component to a load impedance of a load. Multiple instances of the harmonic impedance transformation network and the tuned impedance element can be provided.

Claims (41)

1. A matching network comprising:

an input terminal for receiving an input signal;

a bias feed microstrip structure having a first bias feed end connected to the input terminal and a second bias feed end coupled to a direct current (DC) voltage source, the bias feed microstrip structure having a bias feed microstrip electrical length less than one fifth of a fundamental wavelength of a fundamental frequency component of the input signal, wherein the bias feed microstrip structure provides a quarter-wave transformer for the harmonic frequency component of the input signal;

a harmonic impedance transformation network having a first harmonic impedance transformation network terminal coupled to the input terminal, the harmonic impedance transformation network configured to present, with respect to the input terminal, an optimum impedance for a harmonic frequency component of the input signal;

a tuned impedance element coupled to a second harmonic impedance transformation network terminal of the harmonic impedance transformation network, the tuned impedance element presenting a short circuit impedance at the second harmonic impedance transformation network terminal for the harmonic frequency component and presenting a higher impedance for the fundamental frequency component, wherein the harmonic frequency component is a harmonic of the fundamental frequency component; and

a fundamental impedance transformation network having a first fundamental impedance transformation network terminal coupled to the second harmonic impedance transformation network terminal and a second fundamental impedance transformation network terminal coupled to a first load terminal of a load, the fundamental impedance transformation network configured to match a fundamental impedance transformation network input impedance for the fundamental frequency component to a load impedance of the load.

2. The matching network of claim 1 wherein the matching network is coupled to a switch mode power amplifier.

3. The matching network of claim 2 wherein the switch mode power amplifier is a Class F power amplifier.

4. The matching network of claim 2 wherein the switch mode power amplifier is an inverse Class F power amplifier.

5. The matching network of claim 1 further comprising:

an additional harmonic impedance transformation network interposed between the harmonic impedance transformation network and the load, the additional harmonic impedance transformation network comprising a first additional harmonic impedance transformation network terminal coupled to the second harmonic impedance transformation network terminal and a second additional harmonic impedance transformation network terminal coupled to the first fundamental impedance transformation network terminal; and

an additional tuned impedance element coupled to the second additional harmonic impedance transformation network terminal, the additional tuned impedance element presenting a short circuit at the second additional harmonic impedance transformation network terminal for an additional harmonic frequency component and presenting an additional higher impedance for the fundamental frequency component, wherein the additional harmonic frequency component is an additional harmonic of the fundamental frequency component.

6. The matching network of claim 5 wherein the harmonic frequency component is an odd harmonic of the fundamental frequency component and the additional harmonic frequency component is an even harmonic of the fundamental frequency component.

7. The matching network of claim 1 wherein the matching network is an input matching network of a radio frequency (RF) power amplifier (PA).

8. The matching network of claim 1 wherein the matching network is an output matching network of a RF PA.

9. The matching network of claim 1 wherein the tuned impedance element is an open circuit stub having a tuned impedance element electrical length less than one fifth of the fundamental wavelength.

10. The matching network of claim 1 wherein the matching network is disposed within an integrated circuit package of an integrated circuit.

11. The matching network of claim 1 wherein the bias feed microstrip structure is disposed proximate to a semiconductor device reference plane.

12. The matching network of claim 1 wherein the harmonic frequency component is at least one even harmonic of the fundamental frequency component.

13. The matching network of claim 1 further comprising:

a capacitor having a first capacitor terminal coupled to the second bias feed end and a second capacitor terminal coupled to a ground potential.

14. The matching network of claim 1 wherein the harmonic frequency component is an odd harmonic of the fundamental frequency component.

15. A matching network comprising:

an input terminal for receiving an input signal;

a bias feed microstrip structure having a first bias feed end connected to the input terminal and a second bias feed end coupled to a direct current (DC) voltage source, the bias feed microstrip structure having a bias feed microstrip electrical length less than one fifth of a fundamental wavelength of a fundamental frequency component of the input signal, wherein the bias feed microstrip structure provides a quarter-wave transformer for the harmonic frequency component of the input signal; and

a plurality of harmonic filtering networks configured in series with one another, each of the harmonic filtering networks comprising:

a respective harmonic impedance transformation network for transforming a respective harmonic impedance transformation network input impedance to a respective harmonic impedance transformation network output impedance, wherein at least one harmonic impedance transformation network is configured to present an optimum impedance for at least one respective harmonic frequency component of the input signal; and

a respective tuned impedance element coupled to a respective harmonic impedance transformation network output of the respective harmonic impedance transformation network, the respective tuned impedance element presenting a short circuit impedance at the respective harmonic impedance transformation network output for the at least one respective harmonic frequency component and presenting a higher impedance for the fundamental frequency component, wherein the at least one respective harmonic frequency component is a respective harmonic of the fundamental frequency component.

16. The matching network of claim 15 further comprising:

a fundamental impedance transformation network having a first fundamental impedance transformation network terminal coupled to a final respective harmonic impedance transformation network output and to a load, the fundamental impedance transformation network configured to match a fundamental impedance transformation network input impedance for the fundamental frequency component to a load impedance of the load.

17. The matching network of claim 15 wherein the matching network is disposed within an integrated circuit package of an integrated circuit.

18. A method for matching a source impedance to a load impedance in a matching network comprising:

disposing a bias feed microstrip proximate to and connected with an input terminal of the matching network, the bias feed microstrip coupled to a direct current (DC) voltage source, the bias feed microstrip structure having a bias feed microstrip electrical length less than one fifth of a fundamental wavelength of a fundamental frequency component of an input signal at the input terminal, wherein the bias feed microstrip structure provides a quarter-wave transformer for the harmonic frequency component of the input signal;

transforming a harmonic impedance transformation network input impedance at the input terminal to a harmonic impedance transformation network output impedance, wherein the transforming is configured to present, with respect to the input terminal, an optimum impedance for a harmonic frequency component of the input signal;

filtering a transformed signal using a tuned impedance element to present a short circuit impedance for the harmonic frequency component but not for the fundamental frequency component, wherein the harmonic frequency component is a harmonic of the fundamental frequency component; and

transforming the harmonic impedance transformation network output impedance for the fundamental frequency component to match a load impedance of a load.

19. The method of claim 18 wherein the transforming the harmonic impedance transformation network output impedance to match the load impedance of the load comprises:

additionally transforming the harmonic impedance transformation network output impedance to an additional harmonic impedance transformation network output impedance, wherein the additionally transforming presents an additional optimum impedance for an additional harmonic frequency component of the input signal; and

additionally filtering an additionally transformed signal using an additional tuned impedance element to present an additional short circuit impedance for the additional harmonic frequency component but not for the fundamental frequency component, wherein the additional harmonic frequency component is an additional harmonic of the fundamental frequency component.

20. The method of claim 18 further comprising:

disposing the matching network within an integrated circuit package of an integrated circuit.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2014
From: EMBAR, RAMANUJAM SRINIDHI; NEO, WENG CHUEN EDMUND; WU, YU-TING D.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033199/0890 →