Granted Patent B1

US 9,191,007 · App. 14/310,579 · Granted Nov 17, 2015

Abstract

Claims (98)

1. An integrated circuit comprising:

a latching level shifter coupled to a first power supply voltage, the latching level shifter configured to

store a state during a first phase, and

produce an output voltage based on the state during a high voltage protection phase; and

a logic circuit coupled to the latching level shifter and to a second power supply voltage, the logic circuit configured to receive an input signal and a high voltage protection signal and to drive the latching level shifter in response to the input signal and the high voltage protection signal, the logic circuit further configured to

drive the latching level shifter in the first phase to store the state, wherein

the state is based on the input signal,

the first power supply voltage is set to a first initial voltage level and the second power supply voltage is set to a second initial voltage level during the first phase,

drive the latching level shifter in a second phase subsequent to the first phase, wherein

the first power supply voltage is set to an intermediate voltage level that is greater than the first initial voltage level during the second phase, and

drive the latching level shifter in the high voltage protection phase subsequent to the second phase to produce the output voltage, wherein

the second power supply voltage is set to a first final voltage level that is greater than the second initial voltage level during the high voltage protection phase,

the first power supply voltage is set to a second final voltage level that is greater than the first final voltage level during the high voltage protection phase, and

a voltage difference between the first final voltage level and the second final voltage level is less than a breakdown voltage of the latching level shifter.

2. The integrated circuit of claim 1 , wherein

the logic circuit is triggered to drive the latching level shifter in the first phase in response to receipt of a transitioned value of the input signal,

the logic circuit is triggered to drive the latching level shifter in the second phase in response to expiration of a time period measured from the receipt of the transitioned value of the input signal,

the high voltage protection signal is clear in the first phase and in the second phase, and

the logic circuit is triggered to drive the latching level shifter in the high voltage protection phase in response to the high voltage protection signal being set.

3. The integrated circuit of claim 1 , further comprising

a power supply logic circuit coupled to the first and second power supply voltages, the power supply logic circuit configured to

set the first and second power supply voltages during the first, second, and high voltage protection phases.

4. The integrated circuit of claim 1 , wherein

the second initial voltage level is set at or below the input signal, and

the first initial voltage level is set at a minimum logic voltage necessary for the latching level shifter to store the state.

5. The integrated circuit of claim 1 , wherein

the latching level shifter comprises a first plurality of transistors and a second plurality of transistors, and

the first plurality of transistors are of an opposite connectivity type than the second plurality of transistors.

6. The integrated circuit of claim 5 , wherein

wells of the first plurality of transistors are set at a negative power supply voltage level in the first phase, and

the wells of the first plurality of transistors are set at the first final voltage level in the high voltage protection phase.

7. The integrated circuit of claim 5 , wherein

a well of each of the second plurality of transistors is tied to a source electrode of each of the second plurality of transistors, and

the source electrodes of the second plurality of transistors are coupled to the first power supply voltage.

8. An integrated circuit comprising:

a first transistor having a control gate coupled to an output of a first NAND gate, having a first electrode coupled to an output of a second NAND gate, and having a second electrode;

a second transistor having a control gate coupled to the output of the second NAND gate, having a first electrode coupled to the output of the first NAND gate, and having a second electrode coupled to an output node that provides an output voltage, wherein

a first input of the second NAND gate is coupled to an input signal,

a first input of the first NAND gate is coupled to an inverted version of the input signal, and

the output voltage is based on the input signal;

a third transistor having a control gate coupled to the second electrode of the second transistor, having a first electrode coupled to the output of the second NAND gate, and having a second electrode coupled to the second electrode of the first transistor;

a fourth transistor having a control gate coupled to the second electrode of the first transistor, having a first electrode coupled to the output of the first NAND gate, and having a second electrode coupled to the second electrode of the second transistor;

a fifth transistor having a control gate coupled to the second electrode of the fourth transistor, having a first electrode coupled to the second electrode of the third transistor, and having a second electrode;

a sixth transistor having a control gate coupled to the second electrode of the third transistor, having a first electrode coupled to the second electrode of the fourth transistor, and having a second electrode coupled to the second electrode of the fifth transistor, wherein

the second electrode of the fifth and sixth transistors are further coupled to a first power supply voltage; and

a first inverter having an input coupled to a second input of the first NAND gate and a second input of the second NAND gate and having an output coupled to wells of the first, second, third, and fourth transistors, wherein

the second input of the first NAND gate and the second input of the second NAND gate are coupled to a high voltage protection signal, and

the first NAND gate, the second NAND gate, and the first inverter are further coupled to a second power supply voltage.

9. The integrated circuit of claim 8 , wherein

the first power supply voltage provides a first initial voltage level and the second power supply voltage provides a second initial voltage level in response to receipt of a transitioned value of the input signal,

the first power supply voltage provides an intermediate voltage level that is greater than the first initial voltage level after a time delay subsequent to the receipt of the transitioned value of the input signal, and

the second power supply voltage provides a first final voltage level that is greater than the second initial voltage level and the first power supply voltage provides a second final voltage level that is greater than the first final voltage level in response to the high voltage protection signal being set.

10. The integrated circuit of claim 9 , wherein

a voltage difference between the first final voltage level and the second final voltage level is less than a break down voltage of the first, second, third, fourth, fifth, and sixth transistors.

11. The integrated circuit of claim 9 , wherein

the wells of the first, second, third, and fourth transistors are initially set at a negative power supply voltage level, and

the wells of the first, second, third, and fourth transistors are set at the first final voltage level in response to the high voltage protection signal being set and the second power supply voltage being set to the first final voltage level.

12. The integrated circuit of claim 8 , further comprising

a second inverter having an input coupled to the first input of the second NAND gate and having an output coupled to the first input of the first NAND gate, wherein

the output of the second inverter produces the inverted version of the input signal.

13. The integrated circuit of claim 8 , wherein

a well of the fifth transistor is coupled to the second electrode of the fifth transistor, and

a well of the sixth transistor is coupled to the second electrode of the sixth transistor.

14. The integrated circuit of claim 8 , wherein

the first, second, third, and fourth transistors are of a first conductivity type, and

the fifth and sixth transistors are of a second conductivity type that is opposite the first conductivity type.

15. A method comprising:

driving a latching level shifter in a first mode to store a state, wherein

the latching level shifter is coupled to a first power supply voltage set at a first initial voltage level,

the driving in the first mode is performed by a logic circuit coupled to a second power supply voltage set at a second initial voltage level,

the logic circuit is configured to receive an input signal and a high voltage protection signal, and

the state is based on the input signal;

driving, by the logic circuit, the latching level shifter in a second mode subsequent to the driving in the first mode, wherein

the driving in the second mode comprises

increasing the first power supply voltage to an intermediate voltage level; and

driving, by the logic circuit, the latching level shifter in a high voltage protection mode to produce an output voltage based on the state, wherein

the driving in the high voltage protection mode is performed subsequent to the driving in the second mode,

the driving in the high voltage protection mode comprises

increasing the second power supply voltage to a first final voltage level, and

increasing the first power supply voltage to a second final voltage level subsequent to the increasing the second power supply voltage,

the second final voltage level is greater than the first final voltage level, and

a difference between the first final voltage level and the second final voltage is less than a maximum voltage withstood by the latching level shifter.

16. The method of claim 15 , wherein

the driving in the first mode is triggered in response to receiving a transitioned value of the input signal and the high voltage protection signal being an inactive logic signal,

the driving in the second mode is triggered in response to detecting expiration of a time period measured from the receipt of the transitioned value of the input signal, and

the driving in the high voltage protection mode is triggered in response to detecting the high voltage protection signal is an active logic signal.

17. The method of claim 15 , wherein

the driving in the second mode is triggered in response to detecting the latching level shifter stores an active logic state.

18. The method of claim 15 , wherein

the driving in the second mode is triggered in response to detecting a voltage level of the output voltage corresponds to an active logic state.

19. The method of claim 15 , wherein

the latching level shifter comprises a first set of transistors and a second set of transistors,

the first set of transistors are of an opposite connectivity type as the second set of transistors,

the logic circuit comprises an inverter having an input coupled to the high voltage protection signal and having an output coupled to wells of the first set of transistors, and

the inverter is further coupled to the second power supply voltage.

20. The method of claim 19 , wherein

the driving in the high voltage protection mode further comprises

raising the wells of the first plurality of transistors in response to the increasing the second power supply voltage to the first final voltage level and detecting the high voltage protection signal is an active logic signal.

Assignments (16)