Configurable peripheral componenent interconnect express (PCIe) controller
View Patent ↗In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.
1. A peripheral component interconnect express (PCIe) controller comprising:
an ingress buffer;
an egress buffer;
a first ingress transaction-level selection logic configured to select a first or a second data input signal as an ingress data signal, wherein:
the second data input signal originates from a second PCIe controller; and
the first ingress transaction-level selection logic is enabled by a configuration signal;
a second ingress transaction-level selection logic communicatively coupled to the first ingress transaction-level selection logic, the second ingress transaction-level selection logic configured to:
receive the ingress data signal from the first ingress transaction-level selection logic; and
communicate the ingress data signal to the ingress buffer or a second packet decoder based at least on an ingress transaction steering signal, wherein the ingress transaction steering signal is configured to indicate a priority level associated with the ingress data signal, the priority level having been decoded at a transaction level by a first packet decoder; and
an egress transaction-level selection logic configured to select a first or a second data output signal to an egress data signal, wherein:
the second data output signal originates from the second PCIe controller; and
the egress transaction-level selection logic is enabled by an egress transaction steering signal, the egress transaction steering signal configured to indicate a scheduling order associated with the PCIe controller and the second PCIe controller.
2. The controller of claim 1 , wherein the scheduling order is associated with the priority level.
3. The controller of claim 1 , further comprising a scheduler configured to provide the egress transaction steering signal to the egress transaction-level selection logic.
4. The controller of claim 3 , wherein the scheduler is further configured to provide an egress transaction grant signal to an egress transaction-level selection logic of the second PCIe controller.
5. The controller of claim 1 , further comprising a data link layer communicatively coupled to the first ingress transaction-level selection logic and the egress transaction-level selection logic.
6. The controller of claim 5 , wherein the first packet decoder is an integral part of the data link layer.
7. The controller of claim 1 , further comprising a PCIe link, the PCIe link providing the first data input signal.
8. The controller of claim 1 , wherein the configuration signal is configured to configure the first ingress transaction-level selection logic as part of a startup process.
9. The controller of claim 1 , wherein the priority level is associated with a result of a transaction-level packet inspection process.
10. The controller of claim 9 , wherein the result comprises an identification of a virtual channel, the virtual channel being one of a plurality of virtual channels associated with the ingress data signal.
11. The controller of claim 9 , wherein the result comprises an identification of a traffic class, the traffic class being one of a plurality of traffic classes associated with the ingress data signal.
12. The controller of claim 9 , wherein the result comprises an identification of an address range, the address range being one of a plurality of address ranges associated with the ingress data signal.
13. The controller of claim 1 , wherein the scheduling order comprises a round-robin scheduling order.
14. The controller of claim 1 , wherein the scheduling order comprises a fair share scheduling order.
15. A peripheral component interconnect express (“PCIe”) controller comprising:
a data link layer configured to:
receive a first data input from a PCIe link;
receive a second data input from a second PCIe controller; and
selectively decode a transaction-level packet from either the first or second data input in order to determine a priority level associated with the transaction-level packet; and
generate an ingress transaction steering signal based at least on the priority level; and
a transaction layer configured to:
receive the first or second data inputs from the data link layer;
receive the ingress transaction steering signal from the data link layer;
receive a first data output signal from a fabric communicatively coupled to the PCIe controller;
receive a second data output signal from the second PCIe controller;
selectively communicate the first or second data output signal to the data link layer based at least on a scheduling order associated with the PCIe controller and the second PCIe controller; and
selectively communicate the first or second data inputs to the fabric or the second PCIe controller based at least on the priority level associated with the transaction-level packet, wherein the priority level associated with the PCIe controller is different from the priority level associated with the second PCIe controller.
16. The controller of claim 15 , wherein the scheduling order is associated with a scheduling value, the scheduling value selected from the group comprising: the priority level, a round robin value, and a weighted round robin value.
17. The controller of claim 15 , wherein the priority level is associated with a result of a transaction-level packet inspection process, the result being selected from the group comprising: an identification of a virtual channel, an identification of a traffic class, and an identification of an address range.
18. The controller of claim 15 , wherein the transaction layer is further configured to receive a configuration signal, the configuration signal configured to configure a selection logic associated with the selective communication of the first and second data inputs as part of a startup process.
19. An apparatus comprising:
a processor;
a fabric communicatively coupled to the processor; and
a plurality of PCIe controllers communicatively coupled to the fabric, wherein each of
the plurality of PCIe controllers are communicatively coupled to one or more of its neighboring PCIe controllers, each of the plurality of PCIe controller comprising:
a data link layer configured to:
receive a first data input signal from a PCIe link;
receive a second data input signal from a second PCIe controller, the second PCIe controller being one of the plurality of PCIe controllers and one of the neighboring PCIe controllers; and
selectively decode a transaction-level packet from either the first or second data input signal in order to determine a priority level associated with the transaction-level packet; and
generate an ingress transaction steering signal based at least on the priority level; and
a transaction layer configured to:
receive the first or second data input signal from the data link layer;
receive the ingress transaction steering signal from the data link layer;
receive a first data output signal from a fabric communicatively coupled to the PCIe controller;
receive a second data output signal from the second PCIe controller;
selectively communicate the first or second data output signal to the data link layer based at least on a scheduling order associated with the PCIe controller and the second PCIe controller; and
selectively communicate the first or second data input signals to the fabric or the second PCIe controller based at least on the priority level associated with the transaction-level packet,
wherein the priority level associated with the PCIe controller is different from the priority level associated with the second PCIe controller.
20. The apparatus of claim 19 , wherein the transaction layer is further configured to receive a configuration signal, the configuration signal configured to configure a selection logic associated with the selective communication of the first and second data input signals as part of a startup process.