IP Library Granted Patent US 9,483,373
Granted Patent B2
US 9,483,373 · App. 14/253,427 · Granted Nov 1, 2016

Debug configuration tool with layered graphical user interface

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Quick Facts
Patent No.
US 9,483,373
App. No.
14/253,427
Granted
Nov 1, 2016
Kind
B2
Abstract

A debug configuration tool for configuration of on-chip debug features comprises a database comprising predefined analysis points, each relating to a configurable chip entity, and comprising a configurable condition and a configurable action for the chip entity, a plurality of predefined analysis groups, each relating to a group of configurable chip entities, and comprising a configurable condition and a configurable action for the group of chip entities. The tool comprises a graphical user interface module arranged to display representations of at least some of the analysis points and the analysis groups on different levels of detail, and to receive input from a user to set the configurable conditions and/or actions for the displayed analysis points and the analysis groups. An application program interface module processes data received from the graphical user interface module to obtain debug settings and to communicate the debug settings to a debug target system configuration module.

Claims (38)

1. A debug configuration tool embodied on a non-transitory machine-readable storage medium on a computer for configuration of on-chip debug features of a system-on-a-chip (SoC), the debug configuration tool comprising:

a database comprising:

a plurality of predefined analysis points, each of the analysis points relating to a configurable chip entity, and comprising a configurable condition and a configurable action for the chip entity;

a plurality of predefined analysis groups, each of the analysis groups relating to a group of configurable chip entities, and comprising a configurable condition and a configurable action for the group of chip entities;

a graphical user interface module arranged to:

display representations of at least some of the analysis points and the analysis groups on different levels of detail;

receive input from a user to set the configurable conditions and/or actions for the displayed analysis points and the analysis groups;

an application program interface module arranged to process data received from the graphical user interface module to obtain debug settings and to communicate the debug settings to a debug target system configuration module.

2. The debug configuration tool according to claim 1 , wherein the graphical user interface module is arranged to display the representations of the analysis points and/or analysis groups on different graphical layers reflecting the levels of detail.

3. The debug configuration tool according to claim 2 , wherein each of the analysis groups relates to a chip module and is associated with one or more analysis points that relate to sub-modules of the chip module.

4. The debug configuration tool according claim 3 , wherein the graphical user interface module is arranged to receive input from the user to define a cross triggering event between the analysis points and/or the analysis groups.

5. The debug configuration tool according to claim 4 , wherein the graphical user interface module is arranged to set a specified action of a first analysis point and set a specified condition of a second analysis point, the specified condition being dependent on the specified action.

6. The debug configuration tool according to claim 5 , wherein the application program interface module is arranged to:

set a condition for an analysis group related to a chip module, to obtain a condition setting;

propagate the condition setting top-down to analysis groups and or analysis points of lower level sub-modules of the chip module.

7. The debug configuration tool according to claim 6 , wherein the application program interface module comprises a set of API functions containing subsets of API functions for each of the different levels of detail.

8. The debug configuration tool according to claim 7 , wherein the application program interface module comprises an API function that sets a module condition for an analysis group at a module level for a frame manager of a Data Path Acceleration Architecture block, the module condition being defined by the matching of those frames conforming to a 3-tuple criteria, the 3-tuple comprising a protocol type, a source address and destination address of a frame.

9. The debug configuration tool according to claim 1 , wherein each of the analysis groups relates to a chip module and is associated with one or more analysis points that relate to sub-modules of the chip module.

10. The debug configuration tool according claim 1 , wherein the graphical user interface module is arranged to receive input from the user to define a cross triggering event between the analysis points and/or the analysis groups.

11. The debug configuration tool according to claim 1 , wherein the application program interface module is arranged to:

set a condition for an analysis group related to a chip module, to obtain a condition setting;

propagate the condition setting top-down to analysis groups and or analysis points of lower level sub-modules of the chip module.

12. The debug configuration tool according to claim 1 , wherein the application program interface module comprises a set of API functions containing subsets of API functions for each of the different levels of detail.

13. A method for configuration of on-chip debug features, the method comprising:

defining analysis points, each of the analysis points relating to a configurable chip entity, and comprising a configurable condition and a configurable action for the chip entity;

defining analysis groups, each of the analysis groups relating to a group of configurable chip entities, and comprising a configurable condition and a configurable action for the group of chip entities;

storing the predefined analysis points and predefined analysis groups;

displaying, by means of a graphical user interface, representations of at least some of the analysis points and the analysis groups on different levels of detail;

receiving, by means of the graphical user interface, input from a user to set the configurable conditions and/or actions for the displayed analysis points and the analysis groups;

processing data received from the graphical user interface module to obtain debug settings and

communicating the debug settings to a debug target system configuration module.

14. The method according to claim 13 , wherein the representations of the analysis points and/or analysis groups are displayed on different graphical layers reflecting the levels of detail.

15. The method according to claim 14 , wherein each of the analysis groups relates to a chip module and is associated with one or more analysis points that relate to sub-modules of the chip module.

16. The method according to claim 15 , wherein the graphical user interface is arranged to receive input from the user to define a cross triggering event between the analysis points and/or the analysis groups.

17. The method according to claim 16 , wherein the graphical user interface is arranged to set a specified action of a first analysis point and set a specified condition of a second analysis point, the specified condition being dependent on the specified action.

18. The method according to claim 17 , wherein the method comprises:

setting a condition for an analysis group related to a chip module, to obtain a condition setting;

propagating the condition setting top-down to analysis groups and or analysis points of lower level sub-modules of the chip module.

Assignments (25)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
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PATENT RELEASE Recorded Dec 21, 2015
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