Differential pair sensing circuit structures
View Patent ↗A differential pair sensing circuit ( 300 ) includes control gates ( 306, 316 ) for separately programming a reference transistor ( 350 ) and a chemically-sensitive transistor ( 351 ) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.
1. A differential pair sensing circuit comprising:
a reference field effect transistor comprising a gate electrode coupled to a first voltage; and
a chemically-sensitive field effect transistor (CSFET) comprising a floating gate electrode, a control gate electrode connected to receive a first control gate voltage and capacitively coupled to the floating gate electrode, and a sensing plate electrode capacitively coupled to the floating gate electrode;
where the first voltage and first control gate voltage are separate voltages and where the first control gate voltage adjusts a threshold voltage for the CSFET to control sensitivity or accuracy of the differential pair sensing circuit.
2. The differential pair sensing circuit of claim 1 , where the reference field effect transistor is source-drain connected between a first load resistor and a first reference voltage, and where the CSFET is source-drain connected between a second load resistor and the first reference voltage.
3. The differential pair sensing circuit of claim 1 , where the floating gate electrode is formed with a polysilicon or a metal layer, the control gate electrode is formed with a second polysilicon or metal layer, and the sensing plate electrode is formed with a third polysilicon or metal layer that is located above the second polysilicon or metal layer.
4. The differential pair sensing circuit of claim 1 , comprising a second control gate electrode capacitively coupled to the gate electrode of the reference field effect transistor to apply the first voltage as a second control gate voltage to adjust a threshold voltage for the reference field effect transistor to control sensitivity or accuracy of the differential pair sensing circuit.
5. The differential pair sensing circuit of claim 4 , where the first and second control gate voltages are separate voltages that are connected, respectively, to the control gate electrode and second control gate electrode to adjust the threshold voltages for the reference field effect transistor and CSFET to substantially eliminate threshold voltage mismatch between the reference field effect transistor and CSFET.
6. The differential pair sensing circuit of claim 4 , where the first and second control gate voltages are separate voltages that are connected, respectively, to the control gate electrode and second control gate electrode to adjust the threshold voltages for the reference field effect transistor and CSFET to substantially eliminate threshold voltage mismatch between the reference field effect transistor and CSFET and to substantially eliminate resistance mismatch in the differential pair sensing circuit.
7. The differential pair sensing circuit of claim 1 , further comprising a current mirror circuit coupled to a shared source node of the reference field effect transistor and the CSFET.
8. The differential pair sensing circuit of claim 1 , further comprising first and second gate protection diodes connected, respectively, to the gate of the reference field effect transistor and the gate of the CSFET.
9. A method of forming a chemically-sensitive field effect transistor (CSFET) circuit, comprising:
providing a substrate;
forming a CSFET gate electrode and a reference field effect transistor gate electrode over the substrate;
forming a first capacitor bottom plate layer over and in direct electrical connection with the CSFET gate electrode;
forming a first control gate electrode over the first capacitor bottom plate layer that is capacitively coupled to the CSFET gate electrode;
forming a sense plate layer over the first control gate electrode that is capacitively coupled to the first capacitor bottom plate layer and otherwise electrically isolated from the first control gate electrode;
forming one or more additional first conductors for supplying the first control gate electrode with a first bias voltage to program a desired threshold voltage for the CSFET formed with the CSFET gate electrode; and
forming one or more additional second conductors for coupling a second bias voltage to the reference field effect transistor gate electrode, where the first and second bias voltages are different voltages.
10. The method of claim 9 , where forming the first control gate electrode comprises forming a patterned conductive layer on a dielectric layer formed on the first capacitor bottom plate layer.
11. The method of claim 9 , where the CSFET gate electrode is formed with first polysilicon or metal layer, the first control gate electrode is formed with second polysilicon or metal layer, and the sense plate layer is formed with a third polysilicon or metal layer that is located above the first and second polysilicon or metal layers.
12. The method of claim 9 , further comprising:
forming a second capacitor bottom plate layer over and in direct electrical connection with the reference field effect transistor gate electrode; and
forming a second control gate electrode over the second capacitor bottom plate layer that is capacitively coupled to the reference field effect transistor gate electrode;
where the one or more additional second conductors couple the second bias voltage to the reference field effect transistor gate electrode by supplying the second control gate electrode with the second bias voltage to program a desired threshold voltage for a reference field effect transistor formed with the reference field effect transistor gate electrode.
13. The method of claim 12 , where the reference field effect transistor gate electrode is formed with a polysilicon layer and the second control gate electrode is formed with a first metal interconnect layer.
14. A differential pair sensing device for determining the presence or concentration of one or more target substances in a medium, comprising:
a semiconductor substrate in which is integrated a first field effect transistor and a second field effect transistor having a floating gate electrode;
a capacitor bottom plate conductor formed over the floating gate electrode and directly electrically connected to the floating gate electrode;
first and second capacitor top plate conductors formed over the capacitor bottom plate conductor and capacitively coupled across a dielectric layer to the capacitor bottom plate conductor;
a sense plate layer formed directly over the first and second capacitor top plate conductors and directly electrically connected to the second capacitor top plate conductor, where the sense plate layer is accessible to the medium being measured and able to retain an electrical charge from the medium; and
one or more conductors for supplying a first control gate voltage to the first capacitor top plate conductor to program the second field effect transistor to a desired threshold voltage to adjust sensitivity or accuracy of the differential pair sensing device formed from the first and second field effect transistors.
15. The differential pair sensing device of claim 14 , further comprising:
an additional capacitor bottom plate conductor formed over the first field effect transistor and directly electrically connected to a gate electrode of the first field effect transistor;
an additional top plate conductor formed over the additional capacitor bottom plate conductor and capacitively coupled across a dielectric layer to the additional capacitor bottom plate conductor; and
one or more conductors for supplying a second control gate voltage to the additional capacitor top plate conductor to program the first field effect transistor to a desired threshold voltage to adjust sensitivity and/or accuracy of the differential pair sensing device.