Dual-edge gated clock signal generator
View Patent ↗A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.
1. A clock signal generator for generating a gated clock signal for use with dual-edge triggered circuits, the clock signal generator comprising:
a first detector that receives an input clock signal, a clock gating signal and a feedback of the gated clock signal for generating, when the clock gating signal is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that the input clock signal and the gated clock signal had when the clock gating signal transitioned from asserted to de-asserted; and
a second detector that receives the input clock signal, the clock gating signal and the first detector output signal for generating, when the clock gating signal is de-asserted, as the value of the gated clock signal the value of the input clock signal or the complementary value of the input clock signal as a function of the first detector output signal, and for maintaining, while the clock gating signal is asserted, the value that the gated clock signal had when the clock gating signal transitioned from de-asserted to asserted,
wherein the second detector selects as the value of the gated clock signal the value of the input clock signal if the first detector output signal is de-asserted, and the value of the complement of the input clock signal if the first detector output signal is asserted.
2. The clock signal generator of claim 1 , wherein the first and second detectors comprise first and second asymmetric Muller C-elements respectively.
3. The clock signal generator of claim 1 , wherein the first detector comprises:
a first logic gate that generates a first intermediate signal that is asserted in the case of disjunction of the values of the input clock signal and the gated clock signal;
a second logic gate that generates a second intermediate signal that is de-asserted in the case of conjunction of the values of the input clock signal and the gated clock signal;
a first selector for passing the first or second intermediate signal to the second detector as the first detector output signal while the clock gating signal is asserted; and
a first latch for maintaining the value the first detector output signal had when the clock gating signal transitioned from asserted to de-asserted.
4. The clock signal generator of claim 3 , wherein the first and second logic gates comprise respective XOR and XNOR gates that receive the input clock signal and the gated clock signal, and the complement of the input clock signal and the complement of the gated clock signal.
5. The clock signal generator of claim 3 , wherein the second detector comprises:
a third logic gate that generates a third intermediate signal that is asserted in the case of disjunction of the values of the input clock signal and the first detector output signal;
a fourth logic gate that generates a fourth intermediate signal that is de-asserted in the case of conjunction of the values of the input clock signal and the first detector output signal;
a second selector for passing the third or fourth intermediate signal as the value of the gated clock signal when the clock gating signal is de-asserted; and
a second latch for maintaining the value the second detector output signal had when the clock gating signal transitioned from de-asserted to asserted while the clock gating signal is asserted.
6. A semiconductor device comprising a dual-edge triggered circuit and a clock signal generator for providing a gated clock signal to trigger operation of the dual-edge triggered circuit, the clock signal generator comprising:
a first detector that receives an input clock signal, a clock gating signal and a feedback of the gated clock signal for generating, when the clock gating signal is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that the input clock signal and the gated clock signal had when the clock gating signal transitioned from asserted to de-asserted; and
a second detector that receives the input clock signal, the clock gating signal and the first detector output signal for generating, when the clock gating signal is de-asserted, as the value of the gated clock signal the value of the input clock signal or the complementary value as a function of the first detector output signal, and for maintaining, while the clock gating signal is asserted, the value that the gated clock signal had when the clock gating signal transitioned from de-asserted to asserted,
wherein the second detector selects as the value of the gated clock signal the value of the input clock signal if the first detector output signal is de-asserted, and the value of the complement of the input clock signal if the first detector output signal is asserted.
7. The semiconductor device of claim 6 , wherein the first and second detectors comprise first and second asymmetric Muller C-elements respectively.
8. The semiconductor device of claim 6 , wherein the first detector comprises:
a first logic gate that generates a first intermediate signal that is asserted in the case of disjunction of the values of the input clock signal and the gated clock signal;
a second logic gate that generates a second intermediate signal that is de-asserted in the case of conjunction of the values of the input clock signal and the gated clock signal;
a first selector for passing the first or second intermediate signal to the second detector as the first detector output signal when the clock gating signal is asserted; and
a first latch for maintaining the value the first detector output signal had when the clock gating signal transitioned from asserted to de-asserted.
9. The semiconductor device of claim 8 , wherein the first and second logic gates of the first detector comprise respective XOR and XNOR gates that receive the input clock signal and the gated clock signal and the complement of the input clock signal and the complement of the gated clock signal.
10. The semiconductor device of claim 8 , wherein the second detector comprises:
a third logic gate that generates a third intermediate signal that is asserted in the case of disjunction of the values of the input clock signal and the first detector output signal;
a fourth logic gate that generates a fourth intermediate signal that is de-asserted in the case of conjunction of the values of the input clock signal and the first detector output signal;
a second selector for passing the third or fourth intermediate signal as the value of the gated clock signal when the clock gating signal is de-asserted; and
a second latch for maintaining the value the second detector output signal had when the clock gating signal transitioned from de-asserted to asserted while the clock gating signal is asserted.
11. A method of generating a gated clock signal for use with dual-edge triggered circuit modules, the method comprising:
a first detector receiving an input clock signal, a clock gating signal and a feedback of the gated clock signal;
generating, when the clock gating signal is high (asserted), a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that the input clock signal and the gated clock signal had when the clock gating signal transitioned from asserted to de-asserted;
a second detector receiving the input clock signal, the clock gating signal and the first detector output signal;
generating, when the clock gating signal is de-asserted, as the value of the gated clock signal the value of the input clock signal or the complementary value of the input clock signal as a function of the first detector output signal; and
maintaining, while the clock gating signal is asserted, the value that the gated clock signal had when the clock gating signal transitioned from de-asserted to asserted,
wherein the value of the gated clock signal is selected as the value of the input clock signal if the first detector output signal is de-asserted, and the value of the complement of the input clock signal if the first detector output signal is asserted.
12. The method of claim 11 , wherein first and second asymmetric Muller C-elements are used to generate the first detector output signal and the gated clock signal respectively.
13. The method of claim 11 , further comprising:
generating a first intermediate signal that is asserted in the case of disjunction of the values of the input clock signal and the gated clock signal;
generating a second intermediate signal that is de-asserted in the case of conjunction of the values of the input clock signal and the gated clock signal;
passing the first or second intermediate signal as the first detector output signal when the clock gating signal is asserted; and
maintaining the value the first detector output signal had when the clock gating signal transitioned from asserted to de-asserted.
14. The method of claim 13 , wherein the first and second intermediate signals are produced using detector logic gates comprising respective XOR and XNOR gates that receive the input clock signal and the gated clock signal and the complement of the input clock signal and the complement of the gated clock signal.
15. The method of claim 11 , further comprising:
generating a third intermediate signal that is asserted in the case of disjunction of the values of the input clock signal and the first detector output signal;
generating a fourth intermediate signal that is de-asserted in the case of conjunction of the values of the input clock signal and the first detector output signal;
passing the third or fourth intermediate signal as the value of the gated clock signal when the clock gating signal is de-asserted; and
maintaining the value the second detector output signal had when the clock gating signal transitioned from de-asserted to asserted while the clock gating signal is asserted.