Error correction with secondary memory
View Patent ↗A memory system includes a memory having a plurality of address locations, each address location configured to store data and one or more error correction bits corresponding to the data. A secondary memory includes a plurality of entries, and each entry configured to store an address value of an address location of the memory and one or more error correction bits corresponding to the data stored at the address location of the memory. The error correction bits in the secondary memory can be used to correct errors in a subset of the memory having a different number of storage bits than the error correction bits in the memory.
1. A memory system comprising:
a memory having a plurality of address locations, each address location configured to store data and one or more error correction bits corresponding to the data; and
a secondary memory, wherein the secondary memory includes a plurality of entries, each entry configured to store one or more error correction bits corresponding to the data stored at an address location of the memory, the error correction bits in the secondary memory being used to correct a different number of storage bits in the memory than the error correction bits in the memory.
2. The memory system of claim 1 , wherein each entry of the secondary memory is further configured to store an error correction control value that identifies a type of error correction code to use to correct errors in the corresponding subset of the memory.
3. The memory system of claim 1 , wherein the error correction bits in the secondary memory are used to correct errors in a subset of the memory after a specified number of write operations and/or read operations are performed on memory cells in the subset of the memory.
4. The memory system of claim 1 , wherein different error correction bits are used for different subsets of the data.
5. The memory system of claim 1 , wherein the error correction bits in the secondary memory are changed from first values to second values when a specified criteria for memory cells in the subset of the memory is met, wherein the criteria includes one of a group consisting of: a greater number of errors are found after writing the data than were found during a previous write operation, and a specified number of write operations and/or read operations are performed on memory cells in the subset of the data.
6. The memory system of claim 1 , further comprising:
a memory controller coupled to the memory and to the secondary memory, wherein the memory controller, in response to a read access to a first address location of the memory, is configured to:
determine if a first level of ECC is to be used for the first address location of the memory;
if the first level of ECC is not to be used for the first address location, using the one or more error correction bits stored in the secondary memory to determine if an error is present in the data stored at the first address location; and
if the first level of ECC is to be used for the first address location, using the one or more error correction bits stored in the memory to determine if an error is present in the data stored at the first address location.
7. The memory system of claim 6 , wherein the memory controller, in response to the read access, is further configured to:
marking a block containing the first address location as unusable if the error was not corrected using the error correction bits from the second memory.
8. The memory system of claim 6 , wherein the memory controller, in response to a write access to a second address location of the memory with corresponding write data, is configured to:
store the write data to the second address location;
determine if a second level of ECC is to be used for the second address location of the memory; and
if the second level of ECC is to be used for the second address location, choosing a type of ECC for the secondary memory.
9. The memory system of claim 8 , wherein the memory controller, in response to the write access, is further configured to:
if the second level of ECC is to be used for the second address location, updating ECC information in the secondary memory if a new type of ECC is chosen.
10. The memory system of claim 8 , wherein the memory controller, in response to the write access, is further configured to:
if the second level of ECC is to be used for the first address location, generating one or more error correction bits for the write data based on the type of ECC chosen, and storing the generated one or more error correction bits to the secondary memory.
11. The memory system of claim 1 , wherein the subset of the memory corresponds to one of a page and a block of the memory and the error correction bits in the memory are used to correct errors in a sector of the memory.
12. The memory system of claim 1 , wherein the error correction bits in the memory are used to correct an error in a subset of the memory that is smaller than a page of the memory and the error correction bits in the secondary memory are used to correct one or more errors in a subset that is at least as large as a page of the memory.
13. The memory system of claim 12 , wherein the memory is characterized as a nonvolatile memory and the secondary memory as a random access memory (RAM).
14. The memory system of claim 1 , wherein the memory controller is configured to:
in response to a power down request, store valid entries of the secondary memory to the memory; and
in response to a power up request, restore the valid entries from the memory to the secondary memory.
15. In a memory system, a method comprising:
receiving a request to access to a first address location of a memory, wherein the first address location of the memory stores data and one or more corresponding error correction bits;
in response to the access request:
determining if error correction bits in a secondary memory are to be used to correct errors in the data, wherein the error correction bits in the secondary memory are used to correct a different number of bits in the memory than the error correction bits in the memory;
if the error correction bits in the secondary memory are to be used to correct errors in the data, using the error correction bits stored in the secondary memory to determine if an error is present in at least a portion of the data stored in the memory.
16. The method of claim 15 , further comprising, in response to the access request:
if the error correction bits in the secondary memory are to be used to correct errors in the data, using a page number containing the data to be corrected as an index to a location of the error correction bits in the secondary memory.
17. The method of claim 15 , further comprising:
determining to use the error correction bits in the secondary memory to correct errors in the at least a portion of the data after a specified number of accesses are performed on memory cells in the at least a portion of the data; and
changing the error correction bits in the secondary memory from first values to second values when a specified criteria for memory cells in at least a portion of the data is met, wherein the criteria includes one of a group consisting of: a greater number of errors are found after writing the data than were found during a previous write operation, and another specified number of write operations and/or read operations are performed on memory cells in the at least a portion of the data.
18. A memory system comprising:
a nonvolatile memory having a plurality of address locations, each address location configured to store data and one or more error correction bits corresponding to the data;
a secondary memory, wherein the secondary memory includes a plurality of entries, each entry configured to store an address value of an address location of the memory and one or more error correction bits corresponding to the data stored at the address location of the memory; and
a memory controller coupled to the memory and the secondary memory, wherein the memory controller is configured to:
use a number associated with a size of a respective subsection of the memory to index into the secondary memory;
determine if the error correction bits in the secondary memory are to be used to correct errors in the data; and
if the error correction bits in the secondary memory are to be used to correct errors in the data, use the one or more error correction bits stored at the address location of the memory to determine if an error is present in the data stored at the address location, wherein the amount of data for which errors are corrected using the error correction bits in the secondary memory is different than the amount of data for which errors are corrected using the error correction bits in the nonvolatile memory.
19. The memory system of claim 18 , wherein it is determined to use the error correction bits in the secondary memory to correct errors in a subset of the data after a specified number of write operations and/or read operations are performed on memory cells in the subset of the data.
20. The memory system of claim 18 , wherein the error correction bits in the secondary memory are changed from first values to second values when a specified criteria for memory cells in a subset of the data is met, wherein the criteria includes one of a group consisting of: a greater number of errors are found after writing the data than were found during a previous write operation, and a specified number of write operations and/or read operations are performed on memory cells in the subset of the data.