IP Library Granted Patent US 9,355,985
Granted Patent B2
US 9,355,985 · App. 14/291,547 · Granted May 31, 2016

Microelectronic packages having sidewall-deposited heat spreader structures and methods for the fabrication thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,355,985
App. No.
14/291,547
Granted
May 31, 2016
Kind
B2
Abstract

Microelectronic packages and methods for producing microelectronic packages having sidewall-deposited heat spreader structures are provided. In one embodiment, the method includes providing a package body containing a microelectronic device. A heat spreader structure is printed or otherwise formed over at least one sidewall of the package body. The heat spreader structure is thermally coupled to the microelectronic device and is configured to dissipate heat generated thereby during operation of the microelectronic package.

Claims (43)

1. A method for fabricating a microelectronic package, comprising:

providing a package body including an overmold layer in which a semiconductor die is embedded, the overmold layer having a fan-out region surrounding the semiconductor die;

forming a thermal conduit contained within the package body and extending from a backside of the semiconductor die, at least partially across the fan-out region, and toward a first sidewall of the package body; and

depositing a heat spreader structure onto the first sidewall of the package body, the heat spreader structure thermally coupled to the semiconductor die through the thermal conduit and configured to dissipate heat generated thereby during operation of the microelectronic package.

2. The method of claim 1 wherein forming a thermal conduit comprising printing the thermal conduit from a thermally-conductive ink.

3. The method of claim 1 wherein the overmold layer has backside and an opposing frontside through which the semiconductor die is exposed, wherein the method further comprises producing one or more redistribution layers over the frontside of the overmold layer after formation of the thermal conduit.

4. The method of claim 1 wherein depositing the heat spreader structure comprises:

printing thermally-conductive ink onto a sidewall of the package body; and

sintering the thermally-conducive ink to form the heat spreader structure.

5. The method of claim 1 wherein the heat spreader structure is deposited to include a plurality of spars projecting laterally away from the package body.

6. The method of claim 1 further comprising forming a porous coating over the heat spreader structure having a porosity exceeding the porosity of the material from which the heat spreader structure is formed.

7. The method of claim 1 wherein the microelectronic package comprises first and second package layers bonded in a stacked relationship, and wherein forming comprises forming the heat spreader structure in contact with the first and second package layers.

8. The method of claim 1 wherein providing a package body comprises:

embedding the semiconductor die and the thermal conduit in a molded panel; and

singulating the molded panel to define the package body and to partially remove a peripheral end region of the thermal conduit.

9. The method of claim 1 wherein providing a package body comprises:

placing the semiconductor die on a temporary substrate;

forming the thermal conduit in contact with the semiconductor die and the temporary substrate;

overmolding the semiconductor die and the thermal conduit to yield a molded panel; and

singulating the molded panel to define the package body.

10. The method of claim 9 wherein forming comprises depositing the thermal conduit to have a first portion in contact with the backside of the semiconductor die, a second portion in contact with a sidewall of the semiconductor die, and a third portion in contact with the temporary substrate.

11. The method of claim 9 wherein forming the thermal conduit comprises forming a plurality of thermal conduits in contact with the semiconductor die and the temporary substrate, the plurality of thermal conduits formed as a number of elongated thermally-conductive traces composed of a thermally-conductive ink printed onto the semiconductor die and the temporary substrate.

12. The method of claim 1 wherein depositing the heat spreader structure comprises printing a thermally-conductive ink onto the at least one sidewall in a predetermined pattern.

13. A method for fabricating a microelectronic package, comprising:

forming a thermal conduit in contact with a backside of a semiconductor die contained within a first package layer, the first package layer including a first overmold layer in which the semiconductor die is embedded;

bonding the first package layer to a second package layer in a stacked relationship such that the backside of the semiconductor die faces the second package layer and such that the first and second package layers combine to form a package body, the second package layer containing a microelectronic component embedded within a second overmold layer; and

depositing a heat spreader structure onto a sidewall of the package body, the heat spreader structure contacting the first overmold layer, contacting the second overmold layer, and thermally coupled to the semiconductor die through the thermal conduit.

14. The method of claim 13 wherein the embedded thermal conduit includes an end portion exposed at the sidewall prior to deposition of the heat spreader structure, and wherein the heat spreader structure is deposited in contact with the end portion of the thermal conduit.

15. The method of claim 13 wherein the first package layer is bonded to the second package layer while both the first and second package layers are in panel form to yield a panel stack, and wherein the method further comprises singulating the panel stack to yield the package body and define the sidewall onto which the heat spreader structure is subsequently deposited.

16. A microelectronic package, comprising:

a package body including a first overmold layer having a fan-out region;

a semiconductor die embedded within the first overmold layer and surrounded by the fan-out region;

a thermal conduit embedded within the first overmold layer and extending from a backside of the semiconductor die, at least partially across the fan-out region, and toward a first sidewall of the package body; and

a first heat spreader structure deposited onto the first sidewall of the package body and thermally coupled to the semiconductor die through the thermal conduit.

17. The microelectronic package of claim 16 wherein the package body comprises:

a first package layer including the first overmold layer and further including one or more redistribution layers formed over the first overmold layer; and

a second package layer bonded to the first package layer and facing the backside of the semiconductor die, the thermal conduit located between the redistribution layers and the second package layer.

18. The microelectronic package of claim 16 wherein the first heat spreader structure is deposited in contact with an external surface of the fan-out region.

19. The microelectronic package of claim 16 further comprising a second heat spreader structure deposited over a second sidewall of the package body opposite the first sidewall of the package body.

20. The microelectronic package of claim 16 wherein the thermal conduit comprises:

a first region contacting the backside of the semiconductor die;

a second region contacting a sidewall of the semiconductor die; and

a third region extending laterally away from the semiconductor die and at least partially through the fan-out region.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2014
From: VINCENT, MICHAEL B.; HAYES, SCOTT M.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 033071/0654 →