IP Library Granted Patent US 9,372,724
Granted Patent B2
US 9,372,724 · App. 14/231,789 · Granted Jun 21, 2016

System and method for conditional task switching during ordering scope transitions

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Quick Facts
Patent No.
US 9,372,724
App. No.
14/231,789
Granted
Jun 21, 2016
Kind
B2
Abstract

A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The hardware module stores a first ordering scope identifier at a first storage location of the ordering scope manager. The first ordering scope identifier indicates a first ordering scope that a first task is operating in. The ordering scope manager increments the first ordering scope identifier to create a new ordering scope identifier. In response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, the ordering scope manager provides hint information to the processor core. The processor core transitions from the first ordering scope to the second ordering scope without completing a task switch in response to the hint information.

Claims (42)

1. A method comprising:

storing a first ordering scope identifier at a first storage location of an ordering scope manager, wherein the first ordering scope identifier indicates a first ordering scope that a first task is operating in, the first task being executed by a processor core;

incrementing the first ordering scope identifier to create a new ordering scope identifier;

in response to determining that that the first task is authorized to transition from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, providing hint information from the ordering scope manager to the processor core;

setting a first storage location of the processor core to a first state in response to the hint information; and

in response the first storage location of the processor core being in the first state, transitioning the processor core to the second ordering scope without completing a task switch, otherwise requesting, by the processor core, permission to exit the current ordering scope during the task switch in response to the first storage location being in a second state.

2. The method of claim 1 further comprising:

setting, by the ordering scope manager, a field in an ordering scope table associated with the first task to a first state indicating whether the first task is allowed to transition to the second ordering scope without completing the task switch.

3. The method of claim 2 further comprising:

receiving an indicator that a second storage location of the processor core has been updated in response to the hint information; and

in response to receiving the indicator, setting the field associated with the first task to a second state indicating that the second storage location has been updated.

4. The method of claim 1 further comprising:

storing a third ordering scope identifier at the first storage location, wherein the third ordering scope identifier indicates a third ordering scope that a second task is operating in, the second task being executed by the processor core;

incrementing the third ordering scope identifier to create a fourth ordering scope identifier;

in response to determining that that the second task is authorized to transition from the third ordering scope to a fourth ordering scope associated with the fourth ordering scope identifier, providing second hint information from the ordering scope manager to the processor core; and

in response to the second hint information being provided, transitioning the processor core to the fourth ordering scope without completing a task switch for the second task.

5. The method of claim 1 wherein the first task is authorized to enter the second ordering scope based on the new ordering scope identifier not being found in an ordering scope table.

6. The method of claim 1 wherein the first task is authorized to enter the second ordering scope based on another task in an ordering scope table concurrently executing in the second ordering scope.

7. The method of claim 1 wherein the first task is authorized to enter the second ordering scope when the first task is to concurrently execute the second ordering scope based on a second task exclusively executing the second ordering scope.

8. A method comprising:

executing, at a processor core, a task switch instruction for a task in a current ordering scope; and

transitioning the task from the current ordering scope to an incremental ordering scope of the task without completing a task switch in response a first storage location of the processor core being in a first state, otherwise requesting permission to exit the current ordering scope during the task switch in response to the first storage location being in a second state.

9. The method of claim 8 wherein the first state indicates that the task is authorized to exit the current ordering scope.

10. The method of claim 8 further comprising:

determining that the task is to exclusively execute in the incremental ordering scope in response to information in the task switch instruction.

11. The method of claim 8 further comprising:

determining that the task is to non-exclusively execute in the incremental ordering scope in response to information in the task switch instruction.

12. The method of claim 8 further comprising:

providing, to an ordering scope manager, an update indicator that the processor core is relying on the first storage location of the processor core being in the first state from the processor core.

13. The method of claim 12 further comprising:

providing an ordering scope identifier for the incremental ordering scope to the ordering scope manager in response to transitioning the task from the current ordering scope to the incremental ordering scope.

14. A data processing system comprising:

a processor core, the processor core configured to perform tasks on data packets; and

an ordering scope manager configured to communicate with the processor core, the ordering scope manager configured to store a first ordering scope identifier at a first storage location, wherein the first ordering scope identifier indicates a first ordering scope that a first task is operating in, the ordering scope manager configured to increment the first ordering scope identifier to create a new ordering scope identifier, and in response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, configured to provide hint information to the processor core, wherein the hint information sets a first storage location of the processor core to a first state; and

in response the first storage location of the processor core being in the first state, the processor core is configured to transition from the first ordering scope to the second ordering scope without completing a task switch, otherwise the processor core to request permission to exit the current ordering scope during the task switch in response to the first storage location being in a second state.

15. The data processing system of claim 14 further comprising:

a work scheduler configured to communicate with the processor core and with the ordering scope manager, the work scheduler configured to assign the first task to data of a data packet, and to assign the first task to the processor core.

16. The data processing system of claim 14 wherein the ordering scope manager is further configured to set a field of an ordering scope table associated with the first task to a first state to indicate whether the first task is allowed to transition to the second ordering scope without completing the task switch.

17. The data processing system of claim 14 wherein the processor core is authorized to transition the first task to the second ordering scope based on the new ordering scope identifier not being found in an ordering scope table.

18. The data processing system of claim 14 wherein the processor core is authorized to transition the first task to the second ordering scope based on another task in an ordering scope table being concurrent for the second ordering scope.

19. The data processing system of claim 14 wherein the processor core is authorized to transition the first task to the second ordering scope when the first task is to concurrently execute the second ordering scope based on a second task exclusively executing the second ordering scope.

20. The data processing system of claim 14 wherein the first storage location is local to the ordering scope manager.

Assignments (26)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2025
From: NXP USA, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 072889/0939 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2014
From: XU, ZHENG; JOKINEN, TOMMI M.; MOYER, WILLIAM C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032569/0158 →