SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER
A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer ( 211 ) and a dielectric layer ( 209 ) disposed between the substrate and the semiconductor layer, (b) creating a trench ( 210 ) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure ( 221 ) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer ( 223 ) which comprises a second material and which is disposed on the bottom of the trench.
1 - 18 . (canceled)
19 . A semiconductor device, comprising:
a layer stack comprising a semiconductor layer and a dielectric layer;
a trench which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench adapted to apply stress to the semiconductor layer; and
wherein the semiconductor device is a CMOS device comprising a first region of a first conductivity type, wherein the first-region contains an active region having a transverse edge and a longitudinal edge, wherein the transverse edge is essentially parallel to a direction of current flow through a channel region of the device, wherein the longitudinal edge is essentially perpendicular to the direction of current flow through the channel region of the device, wherein the at least a portion of the trench disposed along the longitudinal edge has been adapted to produce in the active region a tensile stress essentially in direction of current flow, and wherein the at least a portion of the trench disposed along the transverse edge has been adapted to produce in the active region a compressive stress which is essentially in the direction perpendicular to current flow.
20 . A semiconductor device, comprising:
a semiconductor layer;
a trench which extends into the semiconductor layer, the trench adapted to apply stress to the semiconductor layer; and
wherein the semiconductor device is a CMOS device comprising an NMOS region, wherein the NMOS region contains an active region having a transverse edge and a longitudinal edge, wherein the transverse edge is essentially parallel to a direction of current flow through a channel region of the device, wherein the longitudinal edge is essentially perpendicular to the direction of current flow through the channel region of the device, wherein the at least a portion of the trench disposed along the longitudinal edge has been adapted to produce in the active region a tensile stress essentially in direction of current flow, and wherein the at least a portion of the trench disposed along the transverse edge has been adapted to produce in the active region a compressive stress which is essentially in the direction perpendicular to current flow.
21 . The semiconductor device of claim 19 , wherein the at least a portion of the trench disposed along the longitudinal edge has been adapted to comprise a sidewall spacer comprising a first material.
22 . The semiconductor device of claim 21 , wherein the sidewall spacer is not disposed along the at least a portion of the transverse edge.
23 . The semiconductor device of claim 21 , wherein a height of the sidewall spacer is less than a height of the semiconductor layer.
24 . The semiconductor device of claim 19 , wherein the at least a portion of the trench disposed along the longitudinal edge has been adapted to comprise a first sidewall spacer comprising a first material, and the at least a portion of the trench disposed along the transverse edge has not been adapted to comprise the sidewall spacer comprising the first material.
25 . The semiconductor device of claim 19 , wherein the at least a portion of the trench disposed along one of the transverse edge or the longitudinal edge has been adapted to comprise a first sidewall spacer comprising a first material, and the at least a portion of the trench disposed along the other edge has not been adapted to comprise the a sidewall spacer comprising the first material.
26 . The semiconductor device of claim 19 , wherein the semiconductor layer comprises silicon.
27 . The semiconductor device of claim 19 , wherein the semiconductor layer comprises germanium.
28 . The semiconductor device of claim 27 , wherein the semiconductor layer comprises silicon.
29 . A method of making a semiconductor device comprising:
providing a wafer comprising a semiconductor layer overlying a dielectric layer;
forming a trench in the semiconductor layer to define an active region having parallel longitudinal edges, and parallel transverse edges, the longitudinal edges perpendicular to the transverse edges;
adapting at least a portion of the longitudinal edges of the trench to produce a compressive stress in the active region;
adapting at least a portion of the transverse edges of trench to produce a compressive in the active region; and
forming a transistor gate overlying the active region, the transistor gate having a width perpendicular to the transverse edges.
30 . The method of claim 29 , wherein forming the trench comprises forming the trench through the semiconductor layer to expose the dielectric layer.