IP Library Granted Patent US 9,196,576
Granted Patent B2
US 9,196,576 · App. 14/277,801 · Granted Nov 24, 2015

Semiconductor package with stress relief and heat spreader

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Quick Facts
Patent No.
US 9,196,576
App. No.
14/277,801
Granted
Nov 24, 2015
Kind
B2
Abstract

A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle.

Claims (25)

1. A lead frame for a packaged semiconductor device, the lead frame comprising:

a heat sink structure defining a first plane;

a die paddle defining a second plane substantially parallel to and spaced from the first plane, wherein the die paddle comprises two intersecting arms forming an X-shape having four triangular openings, and the heat sink structure comprises four triangular pads corresponding to the four triangular openings in the X-shaped die paddle;

a plurality of tie bars physically and thermally interconnecting the heat sink structure and the die paddle to form a heat sink/paddle sub-assembly, wherein the tie bars connect the die paddle to the heat sink structure at a plurality of locations along the X-shaped die paddle, and wherein the tie bars comprise:

a first plurality of tie bars located at a periphery of the two intersecting arms; and

a second plurality of tie bars located at an intersection of the two intersecting arms; and

a plurality of leads positioned adjacent to the heat sink/paddle sub-assembly.

2. The lead frame of claim 1 , wherein each tie bar comprises a down step between the second plane and the first plane.

3. The lead frame of claim 1 , wherein:

the leads have an outer end located in the first plane, an inner end located in the second plane, and a middle section that extends between and connects the inner and outer ends.

4. A packaged semiconductor device, comprising:

a lead frame including,

a heat sink structure defining a first plane,

a die paddle defining a second plane substantially parallel to and spaced from the first plane, wherein the die paddle comprises two intersecting arms forming an X-shape having four triangular openings, and the heat sink structure comprises four triangular pads corresponding to the four triangular openings in the X-shaped die paddle,

a plurality of tie bars physically and thermally interconnecting the heat sink structure and the die paddle to form a heat sink/paddle sub-assembly, wherein the tie bars connect the die paddle to the heat sink structure at a plurality of locations along the die paddle, and wherein the tie bars comprise:

a first plurality of tie bars located at a periphery of the two intersecting arms; and

a second plurality of tie bars located at an intersection of the two intersecting arms, and

a plurality of leads positioned adjacent to the heat sink/paddle sub-assembly;

a die mounted on the die paddle;

bond wires electrically connecting the die to corresponding ones of the leads; and

mold compound encapsulating the die and the bond wires and at least a portion of the lead frame, wherein a portion of the heat sink structure and a portion of each lead are exposed.

5. The packaged semiconductor device of claim 4 , further comprising:

a heat sink connected to the exposed portion of the heat sink structure.

6. The packaged semiconductor device of claim 4 , wherein the leads have an outer end located in the first plane, an inner end located in the second plane, and a middle section that extends between and connects the inner and outer ends.

7. The packaged semiconductor device of claim 4 , wherein each tie bar comprises a down step between the second plane and the first plane.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: YOW, KAI YUN; EU, POH LENG; LYE, MENG KONG; GE, YOU; MEI, PENGLIN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032907/0770 →