Margin tool for double data rate memory systems
View Patent ↗A tool for testing a double data rate (“DDR”) memory controller to ensure that data strobe transitions are aligned with data eyes to achieve a desired data integrity during data transfers between the memory controller and the memories. After the memory controller completes its training sequence during the initialization process, the tool sweeps the data strobe transition across the data eye. At each timing step during the sweep, several tests may be conducted to check for integrity of functionality. The tool thus generates a pass/fail margin table. The locations of the data strobe transitions selected by the memory controller during its previously run training sequence are then added to this tool-generated margin table. The result is essentially a pseudo data eye, reconstructed including the data strobe transition with the data eye. An inspection of the location of the data strobe transition with the data eye may be utilized to show the range of timing steps available before the data strobe transition would fail to capture valid data from the incoming data eye.
1. A tool for testing double data rate transfers of data between a memory controller and a memory device, the tool comprising:
circuitry for receiving a double data rate strobe placement value indicating where a training sequence performed by the memory controller has placed a double data rate strobe transition within a data eye transferred between the memory device and the memory controller, wherein the double data rate strobe transition is transferred along with the data eye between the memory device and the memory controller;
circuitry for receiving a range of double data rate strobe transition settings that transferred data during a testing of double data rate transfers between the memory controller and the memory device by the tool;
circuitry for comparing the double data rate strobe placement value to the range of double data rate strobe transition settings; and
circuitry for outputting information representing where the double data rate strobe placement value resides within the range of double data rate strobe transition settings.
2. The tool as recited in claim 1 , wherein the training sequence is performed during a power-on initialization of the memory controller.
3. The tool as recited in claim 1 , wherein the memory controller is coupled to the memory device on a printed circuit board, wherein the tool is implemented externally from the printed circuit board.
4. The tool as recited in claim 1 , wherein the double data rate strobe placement value represents an amount of time delay for approximately centering the double data rate strobe transition within the data eye.
5. The tool as recited in claim 1 , wherein the double data rate transfers are transfers of data from the memory device to the memory controller.
6. The tool as recited in claim 1 , wherein the double data rate transfers are transfers of data from the memory controller to the memory device.
7. The tool as recited in claim 1 , wherein the training sequence is performed by the memory controller operating under first physical conditions comprising a first temperature, and wherein the testing by the tool of double data rate transfers between the memory controller and the memory device is performed with the memory controller operating under second physical conditions comprising a second temperature different from the first temperature.
8. The tool as recited in claim 1 , further comprising:
circuitry in the tool for determining an optimal double data rate strobe transition setting based on the range of double data rate strobe transition settings that transferred data during the testing of double data rate transfers between the memory controller and the memory device by the tool;
circuitry in the tool for comparing the double data rate strobe placement value to the optimal double data rate strobe transition setting; and
circuitry in the tool for outputting a difference between the double data rate strobe placement value and the optimal double data rate strobe transition setting.
9. The tool as recited in claim 1 , further comprising circuitry in the tool for storing each of a plurality of double data rate strobe transition settings within the range, whereby each of the plurality of double data rate strobe transition settings within the range comprises either (1) an indication that the double data rate strobe transition setting successfully transferred the data between the memory controller and the memory device, or (2) an indication that the double data rate strobe transition setting failed to successfully transfer the data between the memory controller and the memory device, wherein the circuitry for comparing the double data rate strobe placement value to the range of double data rate strobe transition settings stores a relative location of the double data rate strobe placement value within the stored plurality of double data rate strobe transition settings within the range.
10. The tool as recited in claim 1 , wherein the double data rate strobe transition is generated by the memory device and transferred along with the data eye from the memory device to the memory controller.
11. A method for testing double data rate transfers of data between a memory controller and a memory device, the method comprising:
receiving a double data rate strobe placement value indicating where a training sequence performed by the memory controller has placed a double data rate strobe transition within a data eye transferred between the memory device and the memory controller, wherein the double data rate strobe transition is transferred along with the data eye between the memory device and the memory controller;
receiving a range of double data rate strobe transition settings that transferred data during a testing of double data rate transfers between the memory controller and the memory device;
comparing the double data rate strobe placement value to the range of double data rate strobe transition settings; and
outputting information representing where the double data rate strobe placement value resides within the range of double data rate strobe transition settings.
12. The method as recited in claim 11 , further comprising performing the training sequence during a power-on initialization of the memory controller.
13. The method as recited in claim 11 , wherein the range of double data rate strobe transition settings includes successful and failed data transfers between the memory controller and the memory device.
14. The method as recited in claim 11 , wherein the double data rate strobe placement value represents an amount of time delay for approximately centering the double data rate strobe transition within the data eye.
15. The method as recited in claim 11 , wherein the testing of double data rate transfers between the memory controller and the memory device is performed independently from the training sequence.
16. The method as recited in claim 11 , wherein information representing where the double data rate strobe placement value resides within the range of double data rate strobe transition settings comprises how much the double data rate strobe transition can shift within the data eye before failing to successfully transfer data between the memory controller and the memory device.
17. The method as recited in claim 11 , further comprising determining an optimal double data rate strobe transition setting based on the range of double data rate strobe transition settings that transferred data during the testing of double data rate transfers between the memory controller and the memory device, wherein the optimal double data rate strobe transition setting is not the same as the double data rate strobe placement value determined by the memory controller.
18. A method for designing a double data rate (“DDR”) memory system comprising a DDR memory controller coupled to a DDR memory device, the method comprising:
performing a training sequence comprising the DDR memory controller conducting transfers of test data between the DDR memory device and the DDR memory controller to establish a timing location of an initial DDR data strobe with respect to its corresponding data line coupled between the DDR memory device and the DDR memory controller;
performing a testing process that is operated independently from the training sequence wherein the testing process comprises sweeping a DDR data strobe transition across repeated transfers of the test data between the DDR memory device and the DDR memory controller, the testing process resulting in a data set indicating which of the repeated transfers of the test data correctly and incorrectly captured the test data;
comparing the timing location of the initial DDR data strobe to the data set indicating which of the repeated transfers of the test data correctly and incorrectly captured the test data, the comparison resulting in an output indicating how much margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data; and
adjusting the DDR memory system as a function of the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data, wherein the adjusting of the DDR memory system as a function of the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data further comprises modifying circuitry coupling the DDR memory controller to the DDR memory device to thereby modify the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data, wherein the margin of error is modified so that the timing location of the initial DDR data strobe is substantially centered within a data eye representing a range of DDR data strobe timing locations that would correctly capture the test data transferred on the corresponding data line.
19. The method as recited in claim 18 , further comprising adjusting the timing location of the initial DDR data strobe as a function of the output indicating how much margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data.
20. A method for designing a double data rate (“DDR”) memory system comprising a DDR memory controller coupled to a DDR memory device, the method comprising:
performing a training sequence comprising the DDR memory controller conducting transfers of test data between the DDR memory device and the DDR memory controller to establish a timing location of an initial DDR data strobe with respect to its corresponding data line coupled between the DDR memory device and the DDR memory controller;
performing a testing process that is operated independently from the training sequence wherein the testing process comprises sweeping a DDR data strobe transition across repeated transfers of the test data between the DDR memory device and the DDR memory controller, the testing process resulting in a data set indicating which of the repeated transfers of the test data correctly and incorrectly captured the test data;
comparing the timing location of the initial DDR data strobe to the data set indicating which of the repeated transfers of the test data correctly and incorrectly captured the test data, the comparison resulting in an output indicating how much margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data; and
adjusting the DDR memory system as a function of the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data, wherein the adjusting of the DDR memory system as a function of the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data further comprises modifying circuitry coupling the DDR memory controller to the DDR memory device to thereby modify the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data, wherein the DDR memory system comprises the DDR memory controller coupled to the DDR memory device on a printed circuit board.
21. The method as recited in claim 20 , wherein the training sequence is controlled by a state machine in the DDR memory controller, and wherein the testing process is controlled by a tool implemented externally from the printed circuit board.
22. The method as recited in claim 20 , wherein the adjusting of the DDR memory system further comprises adjusting a design of how the DDR memory device and the DDR memory controller are physically coupled to each other on the printed circuit board.