Laterally diffused metal oxide semiconductor transistors for radio frequency power amplifiers
View Patent ↗Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.
1. A laterally diffused metal oxide semiconductor (LDMOS) transistor comprising:
a substrate having a first surface and a second surface, wherein the first surface comprises an epitaxial layer, and wherein the first surface comprises a drain region, a source region, and a channel region for the LDMOS transistor;
a first region formed from a first dopant of a first type having a first doping concentration, wherein the first region is a continuous region across the source region, the drain region, and the channel region, wherein the first region extends from the first surface into the substrate, stopping at a first depth below the first surface, and wherein the first depth is less than a depth of the epitaxial layer;
a gate electrode over the channel region of the first surface of the substrate;
a second dopant of a second type in the source region, the second dopant having a second doping concentration, wherein the second dopant extends from the first surface into the substrate, stopping at a second depth that is greater than the first depth, wherein the second dopant is laterally diffused under the gate electrode a predetermined distance, and wherein the second type is different than the first type;
a third dopant of the first type in the drain region, the third dopant having a third doping concentration that is greater than the first doping concentration, wherein the third dopant extends from the first surface into the substrate, stopping at a third depth, the third depth being less than the first depth;
a source implant in the source region; and
a drain implant in the drain region.
2. The LDMOS transistor of claim 1 , further comprising a sinker implant in the source region, wherein the sinker implant is used to provide a connection from the source region to the second surface of the substrate.
3. The LDMOS transistor of claim 1 , wherein the first type is an N-type dopant and the second type is a P-type dopant.
4. The LDMOS transistor of claim 1 , wherein the gate electrode is formed from polysilicon.
5. The LDMOS transistor of claim 1 , wherein the epitaxial layer is lightly doped relative to a doping concentration of the substrate.
6. The LDMOS transistor of claim 1 , wherein the second dopant is laterally diffused for substantially an entire length of the gate electrode.
7. The LDMOS transistor of claim 1 , wherein the source implant is an N+ source implant and the drain implant is an N+ drain implant.
8. The LDMOS transistor of claim 1 , wherein the third dopant has no lateral diffusion under the gate electrode.
9. The LDMOS transistor of claim 1 , wherein a net doping concentration of the drain region is greater than either of the first doping concentration or the third doping concentration.
10. A laterally diffused metal oxide semiconductor (LDMOS) transistor comprising:
a substrate having a first surface and a second surface, wherein the first surface comprises an epitaxial layer, and wherein the first surface comprises a drain region, a source region, and a channel region for the LDMOS transistor;
a first region formed from a first N-type dopant having a first doping concentration, wherein the first region is a continuous region across the source region, the channel region, and the drain region, wherein the first region extends from the first surface into the substrate, stopping at a first depth below the first surface, and wherein the first depth is less than a depth of the epitaxial layer;
a gate electrode over the channel region of the first surface of the substrate;
a P-type dopant in the source region of the first surface, wherein the P-type dopant extends from the first surface into the substrate, stopping at a second depth that is greater than the first depth, the P-type dopant having a second doping concentration, wherein the P-type dopant laterally diffused under the gate electrode into the channel region a predetermined distance;
a second N-type dopant in the drain region, the second N-type dopant having a third doping concentration that is greater than the first doping concentration, wherein the second N-type dopant extends from the first surface into the substrate, stopping at a third depth, the third depth being less than the first depth;
an N+ source implant in the source region; and
an N+ drain implant in the drain region.
11. The LDMOS transistor of claim 10 , further comprising a sinker implant in the source region, wherein the sinker implant is used to provide a connection from the source region to the second surface of the substrate.
12. The LDMOS transistor of claim 10 , wherein the gate electrode is formed from polysilicon.
13. The LDMOS transistor of claim 10 , wherein the epitaxial layer is lightly doped relative to a doping concentration of the substrate.
14. The LDMOS transistor of claim 10 , wherein the second dopant is laterally diffused for substantially an entire length of the gate electrode.
15. The LDMOS transistor of claim 10 , wherein the third dopant further is implanted with minimal lateral diffusion under the gate electrode.
16. A laterally diffused metal oxide semiconductor (LDMOS) transistor comprising:
a substrate having a surface, a source region, a drain region, and a channel region;
a first region formed from a first implant of a first conductivity type, wherein the first region is a continuous region across the source region, the drain region, and the channel region, wherein the first region extends from the surface into the substrate, stopping at a first depth below the first surface;
a gate electrode formed over the channel region;
a second implant of a second conductivity type formed in the source region of the substrate, wherein the second implant extends from the surface into the substrate, stopping at a second depth that is greater than the first depth, and the second implant is laterally diffused under the gate electrode into the channel region a predetermined distance; and
a third implant of the first conductivity type that extends from the surface into the substrate in the drain region of the substrate, wherein the third implant stops at a third depth, the third depth being less than the first depth.
17. The LDMOS transistor of claim 16 , further comprising:
an N+ source implant in the source region a first predetermined distance from the gate electrode; and
an N+ drain implant in the drain region a second predetermined distance from the gate electrode,
wherein the third implant is formed in the channel region from an edge of the gate electrode to the N+ drain implant.
18. The LDMOS transistor of claim 16 , wherein the second implant is laterally diffused under the gate electrode for substantially an entire length of the gate electrode.
19. The LDMOS transistor of claim 16 , wherein the first implant and the third implant each comprises an N-type dopant, and the second implant comprises a P-type dopant.