IP Library Granted Patent US 9,401,339
Granted Patent B2
US 9,401,339 · App. 14/277,343 · Granted Jul 26, 2016

Wafer level packages having non-wettable solder collars and methods for the fabrication thereof

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Quick Facts
Patent No.
US 9,401,339
App. No.
14/277,343
Granted
Jul 26, 2016
Kind
B2
Abstract

Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

Claims (41)

1. A method for producing a wafer level package, the method comprising:

forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer, the patterned metal level comprising a first alloy;

before or after forming solder mask openings in the solder mask layer, producing non-wettable solder collars in contact with and extending partially over the exposed regions of the patterned metal level, the non-wettable solder collars produced from a second alloy different than the first alloy; and

depositing solder balls into the solder mask openings and onto the non-wettable solder collars and performing a solder ball reflow process such that, after solder ball reflow, circumferential clearances are provided around base portions of the solder balls and the sidewalls of the solder mask layer defining the solder mask openings, the circumferential clearances comprising annular gaps separating the portions of the solder balls contacting the non-wettable solder collars from the sidewalls of the solder mask layer defining the solder mask openings.

2. The method of claim 1 wherein producing comprises producing the non-wettable solder collars to include central openings in which the solder balls seat, the solder balls contacting the exposed regions of the patterned metal level through the central openings after deposition and reflow of the solder balls.

3. The method of claim 1 wherein producing comprises producing the non-wettable solder collars to have heights equivalent to or less than a thickness of the solder mask layer.

4. The method of claim 1 wherein the second alloy comprises titanium tungsten.

5. The method of claim 1 wherein producing comprises:

sputter depositing a non-wettable alloy layer on the patterned metal level; and

patterning the non-wettable alloy layer to define the non-wettable solder collars.

6. The method of claim 1 further comprising depositing the solder mask layer over the patterned metal level prior to producing the non-wettable solder collars.

7. The method of claim 6 wherein producing comprises dispensing a non-solder-wettable epoxy over the patterned metal level to form the non-wettable solder collars.

8. The method of claim 6 wherein producing comprises producing the non-wettable solder collars to be fully contained within the solder mask openings.

9. The method of claim 1 further comprising producing at least one redistribution layer over a semiconductor die embedded in a molded package body prior to forming the solder mask openings in the solder mask layer, the at least one redistribution layer containing the solder mask layer and the patterned metal level.

10. A method for producing a wafer level package, the method comprising:

forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer;

before or after forming solder mask openings in the solder mask layer, producing non-wettable solder collars in contact with and extending partially over the exposed regions of the patterned metal level;

depositing solder balls into the solder mask openings and onto the non-wettable solder collars and performing a solder ball reflow process such that, after solder ball reflow, circumferential clearances are provided around base portions of the solder balls and the sidewalls of the solder mask layer defining the solder mask openings, the circumferential clearances comprising annular gaps separating the portions of the solder balls contacting the non-wettable solder collars from the sidewalls of the solder mask layer defining the solder mask openings; and

depositing the solder mask layer over the patterned metal level after producing the non-wettable solder collars.

11. The method of claim 10 wherein forming comprises forming solder mask openings in the solder mask layer exposing regions of the patterned metal level underlying the solder mask layer and at least partially exposing the non-wettable solder collars.

12. The method of claim 11 wherein forming comprises forming the solder mask openings to partially expose the non-wettable solder collars, while leaving outer peripheral portion of the non-wettable solder collars covered by the solder mask layer.

13. The method of claim 10 wherein producing comprises producing the non-wettable solder collars to include central openings in which the solder balls seat, the solder balls contacting the exposed regions of the patterned metal level through the central openings after deposition and reflow of the solder balls.

14. The method of claim 10 wherein producing comprises producing the non-wettable solder collars to have heights equivalent to or less than a thickness of the solder mask layer.

15. The method of claim 10 wherein the patterned metal level comprises a first alloy, and wherein producing comprises producing the non-wettable solder collars from a second alloy different than the first alloy.

16. The method of claim 10 wherein producing comprises:

sputter depositing a non-wettable alloy layer on the patterned metal level; and

patterning the non-wettable alloy layer to define the non-wettable solder collars.

17. The method of claim 10 further comprising producing at least one redistribution layer over a semiconductor die embedded in a molded package body prior to forming the solder mask openings in the solder mask layer, the at least one redistribution layer containing the solder mask layer and the patterned metal level.

18. A method for producing a wafer level package, the method comprising:

sputter depositing a non-solder-wettable alloy layer over a patterned metal level having a plurality of solder ball contact points thereon, the patterned metal level comprising the last metal level included in at least one redistribution layer produced over a semiconductor die embedded in a molded package body;

patterning the non-solder wettable alloy layer to define non-wettable solder collars circumscribing the plurality of solder ball contact points and having central openings through which the plurality of solder ball contact points are exposed;

depositing solder balls onto the non-wettable solder collars; and

heating the solder balls to a predetermined reflow temperature to produce reflowed solder balls contacting the plurality of solder ball contact points through the central openings of the non-wettable solder collars.

19. The method of claim 18 further comprising:

before or after patterning the non-solder wettable alloy layer, depositing a dielectric layer over the patterned metal level; and

forming openings in the dielectric layer exposing the plurality of solder ball contact points;

wherein the solder balls are deposited onto the non-wettable solder collars to have reduced sizes relative to the openings formed in the dielectric layer such that circumferential clearances are created between the plurality of solder balls and sidewalls of the dielectric layer defining the openings; and

wherein heating is performed under process conditions sufficient to maintain circumferential clearances between the plurality of solder balls and sidewalls of the dielectric layer defining the openings.

20. The method of claim 18 further comprising:

forming solder mask openings in a solder mask layer deposited over the patterned metal level to expose the plurality of solder ball contact points through the solder mask layer; and

depositing and heating the solder balls under controlled reflow conditions providing annular air gaps separating the portions of the solder balls contacting the non-wettable solder collars from the sidewalls of the solder mask layer defining the solder mask openings.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2014
From: YAP, WENG F.; MAGNUS, ALAN J.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 032887/0032 →