MEMORY ACCESS CONTROLLER, DATA PROCESSING SYSTEM, AND METHOD FOR MANAGING DATA FLOW BETWEEN A MEMORY UNIT AND A PROCESSING UNIT
A memory access controller for managing data flow between a memory unit and a processing unit is described. The memory access controller comprises an addressing unit and an unpacking unit. The addressing unit may receive an address from said processing unit and select a data location within said memory unit in dependence on that address. The unpacking unit may read a first word from the selected data location, unpack the first word into a second word by applying a data conversion scheme which depends on the received address, and provide the second word to the processing unit. The data conversion scheme may comprise, for at least one possible address, a pixel format conversion. A data processing system and a method are also proposed.
1 . A memory access controller for managing data flow between a memory unit and a processing unit, said memory access controller comprising an addressing unit and an unpacking unit,
said addressing unit being arranged to receive an address from said processing unit and to select a data location within said memory unit in dependence on said address,
said unpacking unit being arranged to read a first word from said selected data location, to unpack said first word into a second word by applying a data conversion scheme which depends on said address, and to provide said second word to said processing unit.
2 . The memory access controller of claim 1 , said second word being larger than said first word.
3 . The memory access controller of claim 1 , said data conversion scheme comprising, for at least one possible address, a pixel format conversion.
4 . The memory access controller of claim 1 , said address received from said processing unit comprising a page number and an offset, said data conversion scheme depending on said page number but not on said offset.
5 . The memory access controller of claim 1 , said unpacking unit being arranged to unpack a group of at least two words in parallel, each word of the group having the size of said first word.
6 . The memory access controller of claim 1 , further comprising a packing unit arranged to receive a third word from said processing unit, to pack said third word into a fourth word by applying a data back-conversion scheme which depends on said received address, and to write said fourth word to said selected memory location.
7 . The memory access controller of claim 6 , said data back-conversion being an inverse of said data conversion.
8 . The memory access controller of claim 6 , said data back-conversion scheme comprising, for at least one possible address, a pixel format back-conversion.
9 . The memory access controller of claim 6 , said address received from said processing unit comprising a page number and an offset, said data back-conversion scheme depending on said page number but not on said offset.
10 . The memory access controller of claim 6 , said packing unit being arranged to pack a group of at least two words in parallel, each word of the group having the size of said third word.
11 . A data processing system comprising a memory unit, a processing unit, and a memory access controller, said memory access controller being connected between said memory unit and said processing unit and arranged to manage data flow between said memory unit and said processing unit, said memory access controller comprising an addressing unit and an unpacking unit,
said addressing unit being arranged to receive an address from said processing unit and to select a data location within said memory unit in dependence on said address,
said unpacking unit being arranged to read a first word from said selected data location, to unpack said first word into a second word by applying a data conversion scheme which depends on said address, and to provide said second word to said processing unit.
12 . The data processing system of claim 11 , said unpacking unit being arranged to unpack a group of at least two words in parallel, each word of the group having the size of said first word, said processing unit being arranged to process the group of unpacked words in parallel.
13 . The data processing system of claim 12 , said processing unit being connected to said memory access controller via a bus, said bus being arranged to transfer the group of unpacked words in parallel.
14 . The data processing system of claim 11 , or said processing unit being a general purpose processor, a Direct-Memory-Access controller, a graphics processing unit, a display controller, an image decoder, or an image encoder.
15 . A method for managing data flow between a memory unit and a processing unit, comprising:
receiving an address from said processing unit;
selecting a data location within said memory unit in dependence on said address;
reading a first word from said selected data location;
unpacking said first word into a second word by applying a data conversion scheme which depends on said address; and
providing said second word to said processing unit.