Multiplying digital to analog converter (MDAC) with error compensation and method of operation
View Patent ↗The present disclosure provides methods and circuits for compensating reference shifting error. A compensation reference voltage is applied to an error compensation circuit, which is coupled to a multiplying circuit. A compensation parasitic capacitance is induced in the error compensation circuit. The compensation parasitic capacitance is configured to negate a parasitic capacitance induced in the multiplying circuit.
1. A multiplying digital to analog converter (MDAC) circuit comprising:
a multiplying circuit configured to receive an input voltage and output an output voltage, wherein
a first parasitic capacitance is induced in the multiplying circuit; and
an error compensation circuit coupled to the multiplying circuit, wherein
the error compensation circuit is configured to receive a compensation reference voltage,
a second parasitic capacitance is induced in the error compensation circuit, and
the second parasitic capacitance is configured to negate the first parasitic capacitance.
2. The MDAC circuit of claim 1 , wherein
the first parasitic capacitance causes a reference shifting error that affects the output voltage,
the second parasitic capacitance causes a compensation factor that further affects the output voltage, and
the compensation factor is configured to negate the reference shifting error.
3. The MDAC circuit of claim 1 , wherein
the compensation reference voltage is selected from a set of voltages based on a range within which the input voltage falls.
4. The MDAC circuit of claim 1 , wherein
the compensation reference voltage is one of a set of voltages that includes a positive reference voltage, a common mode voltage, and a negative reference voltage.
5. The MDAC circuit of claim 1 , wherein
the multiplying circuit is configured to receive a reference voltage, and
the compensation reference voltage is complementary to the reference voltage.
6. The MDAC circuit of claim 1 , wherein
the input voltage is a differential input voltage,
the output voltage is a differential output voltage, and
the compensation reference voltage is a differential reference voltage.
7. The MDAC circuit of claim 1 , further comprising
a second error compensation circuit coupled to the multiplying circuit and the error compensation circuit, wherein
the second error compensation circuit is configured to receive the input voltage and a common mode voltage,
a third parasitic capacitance is induced in the multiplying circuit,
a fourth parasitic capacitance is induced in the second error compensation circuit, and
the fourth parasitic capacitance is configured to negate the third parasitic capacitance.
8. The MDAC circuit of claim 1 , wherein
the first and second parasitic capacitances are induced during a first clock phase, and
the first and second parasitic capacitances affect the output voltage during a second clock phase.
9. The MDAC circuit of claim 8 , wherein
the first clock phase is a sampling phase, and
the second clock phase is an amplifying phase.
10. The MDAC circuit of claim 1 , wherein the MDAC circuit is used in a pipelined analog to digital converter.
11. A multiplying digital to analog converter (MDAC) circuit comprising:
a multiplying circuit, wherein
the multiplying circuit is configured to receive an input voltage and output an output voltage; and
an error compensation circuit coupled to the multiplying circuit, wherein
the error compensation circuit includes
a first topology during a first phase, wherein the first topology includes
a first compensation capacitor coupled between a first node and a second node,
the first node is coupled to a common mode voltage node via a first switch that is closed,
the second node is coupled to a compensation reference voltage node via a second switch that is closed,
the first node and the second node are coupled to a third switch that is open,
the second node and a third node of the multiplying circuit are coupled to a fourth switch that is open,
the third node has a first parasitic capacitance, and
the second node has a compensation parasitic capacitance, and
a second topology during a second phase, wherein the second topology includes
a first connection between the first node and the second node formed by the third switch that is closed,
the first and second switches are open,
a second connection between the second node and the third node formed by the fourth switch that is closed, and
the compensation parasitic capacitance negates the first parasitic capacitance.
12. The MDAC circuit of claim 11 , wherein
the multiplying circuit includes an amplifier configured to output the output voltage, and
the second connection between the second node and the third node is coupled to an input terminal of the amplifier.
13. The MDAC circuit of claim 11 , wherein
the compensation reference voltage is complementary to a reference voltage applied in the multiplying circuit.
14. The MDAC circuit of claim 11 , wherein
the input voltage is a differential input voltage,
the output voltage is a differential output voltage, and
the reference voltage is a differential reference voltage.
15. The MDAC circuit of claim 11 , further comprising
a second error compensation circuit coupled to the multiplying circuit and the error compensation circuit, wherein
the second error compensation circuit includes
a third topology during the first phase, wherein the third topology includes
a first capacitor coupled between a fourth node and a fifth node,
the fourth node is coupled to the common mode voltage node via a fifth switch that is closed,
the fifth node is coupled to the input voltage via a sixth switch that is closed,
the fourth node and the fifth node are coupled to a seventh switch that is open,
the fourth node and the third node of the multiplying circuit are coupled to a eighth switch that is open,
the third node has a second parasitic capacitance, and
the fifth node has a second compensation parasitic capacitance; and
a fourth topology during the second phase, wherein the fourth topology includes
a third connection between the fourth node and the fifth node formed by the seventh switch that is closed,
the fifth and sixth switches are open,
a fourth connection between the fourth node and the third node formed by the eighth switch that is closed, and
the second compensation parasitic capacitance negates the second parasitic capacitance.
16. The MDAC circuit of claim 11 , wherein the error compensation circuit further comprises
the compensation reference voltage node coupled to a positive reference voltage via a fifth switch, coupled to a common mode voltage via a sixth switch, and coupled to a negative reference voltage via a seventh switch, and
the fifth, sixth, and seventh switches controlled by a switch control according to a value of the input voltage.
17. A method for compensating reference shifting error, the method comprising:
applying a compensation reference voltage to an error compensation circuit, wherein the error compensation circuit is coupled to a multiplying circuit;
inducing a compensation parasitic capacitance in the error compensation circuit during a first phase of the error compensation circuit; and
introducing the compensation parasitic capacitance to the multiplying circuit during a second phase of the error compensation circuit, wherein
the compensation parasitic capacitance is configured to negate a parasitic capacitance induced in the multiplying circuit.
18. The method of claim 17 , wherein
the parasitic capacitance causes a reference shifting error that affects an output voltage produced by the multiplying circuit,
the compensation parasitic capacitance causes a compensation factor that further affects the output voltage, and
the compensation factor is configured to negate the reference shifting error.
19. The method of claim 17 , wherein
the compensation reference voltage is complementary to a reference voltage applied to the multiplying circuit.
20. The method of claim 17 , further comprising
determining the compensation reference voltage based on an input voltage applied to the multiplying circuit, wherein the determining the compensation reference voltage further comprises
determining a particular range of voltages within which the input voltage falls, wherein
the particular range is associated with a compensation reference voltage variable; and
selecting the compensation reference voltage from a set of voltages based on the compensation reference voltage variable.