Controller, SATA system and method of operation therefor
A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system is described. The controller comprises a hardware processor arranged to: receive a plurality of SATA data frames; identify a first primitive sequence in at least one of the plurality of SATA data frames that adversely affects a performance of the SATA system; and replace the identified first primitive sequence with a second primitive sequence in response thereto.
1. A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system, wherein the controller comprises a hardware processor arranged to:
receive a plurality of SATA data frames;
determine that a sequence of primitives in at least one of the plurality of SATA data frames matches a first primitive sequence stored at a register, the sequence of primitives received without errors and including more than one primitive, wherein the first primitive sequence adversely affects a data transfer performance of the SATA system; and
replace the sequence of primitives with a second primitive sequence to improve the data transfer performance of the SATA system relative to the first primitive sequence.
2. The controller of claim 1 further comprising at least one primitive sequence queue module operably coupled to the hardware processor and arranged to provide the second primitive sequence to replace the first primitive sequence.
3. The controller of claim 1 wherein the controller further comprises a Primitive Modification Control (PMC) module operably coupled to the hardware processor and arranged to compare a primitive message of at least one SATA data frame with stored primitive data.
4. The controller of claim 3 wherein the PMC module is arranged to compare as a first input a primitive sequence from the plurality of SATA data frames with a second input of a primitive sequence output from a current primitive sequence queue (CPSQ) module and assume responsibility in outputting a transmission from the controller in response to detecting a match of said first input and said second input.
5. The controller of claim 4 , wherein the PMC module is operably coupled to a modified primitive sequence queue (MPSQ) module and arranged to output a primitive sequence from the MPSQ module in response to detecting the match.
6. The controller of claim 5 , wherein the PMC module is arranged to prepare an entry to an Exception Status Queue (ESQ) module coupled thereto, with information about the primitive sequence from the MPSQ module.
7. The controller of claim 4 , wherein the PMC module comprises a masking register for masking a transition from outputting the received plurality of SATA data frames to outputting the second primitive sequence.
8. The controller of claim 4 , wherein a last entry in the current primitive sequence queue comprises a ‘last entry’ indicator.
9. The controller of claim 3 , wherein the PMC module comprises a frame tag input that functions as a frame identifier and includes control information.
10. The controller of claim 1 wherein the hardware processor identifies the first primitive sequence that adversely affects a performance of the SATA system by detecting an error or performance limiting event in at least one of: the primitive or primitive sequence.
11. The controller of claim 10 , wherein in response to detecting an error or performance limiting event the hardware processor diverts the sequence comprising the primitive or primitive sequence in error to a software processor for handling of the sequence.
12. The controller of claim 1 , wherein the hardware processor is arranged to replace the sequence of primitives with the second primitive sequence in response to a mode bit being activated.
13. A serial advanced technology attachment (SATA) system comprising the controller of claim 1 .
14. The controller of claim 1 , wherein:
the register comprises a programmable current primitive sequence queue (CPSQ) configured to store the first primitive sequence that needs modification; and
wherein the hardware processor comprises:
a programmable modified primitive sequence queue (MPSQ) configured to store the second primitive sequence to replace the sequence of primitives; and
a primitive modification controller (PMC) configured to transmit the second primitive sequence from the MPSQ in response to detecting the sequence of primitives in the at least one of the plurality of SATA data frames matches the first primitive sequence stored at the CPSQ.
15. The controller of claim 1 , wherein the sequence of primitives in the at least one of the plurality of SATA data frames is replaced in its entirety with the second primitive sequence.
16. A method of performance improvement in a serial advanced technology attachment (SATA) system, the method comprising:
receiving a plurality of SATA data frames including a sequence of primitives received without errors;
determining that the sequence of primitives matches a first primitive sequence that adversely affects a data transfer performance of the SATA system, the first primitive sequence stored at a register and including more than one primitive; and
replacing the sequence of primitives with a second primitive sequence to improve the data transfer performance of the SATA system relative to the first primitive sequence.
17. The method of claim 16 , further comprising:
storing the first primitive sequence at a programmable current primitive sequence queue (CPSQ), to specify the sequence of primitives that needs modification; and
storing the second primitive sequence at a programmable modified primitive sequence queue (MPSQ).
18. The method of claim 16 , wherein the sequence of primitives in the at least one of the plurality of SATA data frames is replaced in its entirety with the second primitive sequence.
19. A non-transitory computer program product comprising executable program code stored therein for performance improvement in a serial advanced technology attachment (SATA) system, the program code comprising instructions operable for performing the method comprising:
receiving a plurality of SATA data frames including a sequence of primitives received without errors;
determining that the sequence of primitives matches a first primitive sequence that adversely affects a data transfer performance of the SATA system, the first primitive sequence stored at a register and including more than one primitive; and
replacing the sequence of primitives with a second primitive sequence to improve the data transfer performance of the SATA system relative to the first primitive sequence.
20. The non-transitory computer program product of claim 19 , further comprising instructions to:
store the first primitive sequence at a programmable current primitive sequence queue (CPSQ), to specify the sequence of primitives that needs modification; and
store the second primitive sequence at a programmable modified primitive sequence queue (MPSQ).