Method for improving E-beam lithography gate metal profile for enhanced field control
View Patent ↗A semiconductor device is provided which includes a GaN-on-SiC substrate ( 50 - 51 ) and a multi-layer passivation stack ( 52 - 54 ) in which patterned step openings ( 76 ) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode ( 74 ) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.
1. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a multi-layer dielectric stack on the substrate;
patterning a multi-layer resist stack on the multi-layer dielectric stack to define a first etch opening over the multi-layer dielectric stack;
applying a first wet etch process to remove a top aluminum oxide layer in the multi-layer dielectric stack that is exposed by the first etch opening;
applying a reactive-ion etch process to remove a middle silicon nitride layer in the multi-layer dielectric stack that is exposed by the first etch opening and to laterally enlarge a bottom portion of the first etch opening, thereby exposing a portion of the top aluminum oxide layer; and
applying a second wet etch process to remove a bottom aluminum oxide layer in the multi-layer dielectric stack that is exposed by the first etch opening and the exposed portion of the top aluminum oxide layer, thereby forming a stepped opening in the multi-layer dielectric stack which exposes a gate contact surface of the substrate; and
forming a conductive gate electrode in contact with the gate contact surface of the substrate and in the stepped opening to form a contact base portion with one or more gate ledges, the conductive gate electrode comprising gate electrode sidewall extensions that are vertically spaced above the one or more gate ledges.
2. The method of claim 1 , where forming the multi-layer dielectric stack comprises sequentially depositing a bottom layer of aluminum oxide on the substrate, a middle layer of silicon nitride on the bottom layer, and a top layer of aluminum oxide on the middle layer.
3. The method of claim 1 , where patterning the multi-layer resist stack comprises:
depositing a bottom resist layer on the multi-layer dielectric stack;
depositing a middle resist layer on the bottom resist layer;
depositing a top resist layer on the middle resist layer;
exposing the top resist layer, middle resist layer, and bottom resist layer with one or more exposure steps; and
developing the top, middle, and bottom resist layers of the multi-layer resist stack with one or more developer steps to pattern the first etch opening which exposes a portion of the multi-layer dielectric stack for etching.
4. The method of claim 1 , where patterning the multi-layer resist stack comprises applying one or more e-beam lithography steps to pattern the first etch opening in the multi-layer resist stack.
5. The method of claim 1 , where forming the conductive gate electrode comprises:
evaporating gate metal into the first etch opening and the patterned opening to form the conductive gate electrode comprising:
the contact base portion with one or more gate ledges in contact with the stepped opening and the gate contact surface of the substrate, and
gate electrode sidewall extensions that are vertically spaced above the one or more gate ledges.
6. The method of claim 1 , where patterning a multi-layer resist stack comprises forming a multi-layer e-beam gate electrode resist mask overlying the multi-layer dielectric stack with a gate electrode opening having a narrow bottom opening portion, wider middle opening portion, and narrow top opening portion.
7. The method of claim 1 , where the substrate comprises a gallium nitride layer formed on a top surface of the substrate.
8. The method of claim 1 , where applying the first wet etch process removes a portion of the top aluminum oxide layer to expose a horizontal ledge of the middle silicon nitride layer in the multi-layer dielectric stack, where the horizontal ledge is between 100 and 500 Angstroms wide.
9. The method of claim 8 , where forming the conductive gate electrode comprises forming a contact base portion with a gate ledge contacting the horizontal ledge of the middle dielectric layer and forming the gate electrode sidewall extensions that are vertically spaced above the gate ledge.
10. A method for forming a gallium nitride semiconductor device, comprising:
providing a semiconductor substrate comprising a gallium nitride surface layer;
covering the semiconductor substrate with a plurality of dielectric layers;
providing a patterned multi-layer resist stack overlying the plurality of dielectric layers with a mask opening located above the semiconductor substrate, the mask opening comprising a narrow bottom opening portion which exposes a top portion of the plurality of dielectric layers, a wider middle opening portion aligned over the narrow bottom opening portion, and a top opening portion that is aligned over and narrower than the middle opening portion;
etching through a top dielectric layer from the plurality of dielectric layers exposed by the narrow bottom opening portion of the patterned multi-layer resist stack with a first wet etch process to form a first opening in the top dielectric layer having a first width which exposes a middle dielectric layer from the plurality of dielectric layers;
etching through the middle dielectric layer from the plurality of dielectric layers exposed by the first opening with a reactive ion etch process to form a second opening in the middle dielectric layer having the first width which exposes a bottom dielectric layer from the plurality of dielectric layers while simultaneously widening the narrow bottom opening portion of the patterned multi-layer resist stack to expose an additional portion of the top dielectric layer;
etching through the bottom dielectric layer from the plurality of dielectric layers exposed by the second opening with a second wet etch process to form a third opening in the bottom dielectric layer having the first width which exposes a first portion of the gallium nitride surface layer while simultaneously widening the first opening in the top dielectric layer to form a wider first opening;
forming a stepped field plate structure in contact with at least part of the exposed first portion of the gallium nitride surface layer by filling the wider first opening, second opening, and third opening with one or more conductive layers, where the stepped field plate structure comprises a gate length contact base having a gate length and one or more gate ledges, and gate electrode sidewall extensions formed to be vertically spaced apart from the plurality of dielectric layers.
11. The method of claim 10 , where providing the patterned multi-layer resist stack comprises:
forming a bottom resist layer on top of the plurality of dielectric layers;
forming a middle resist layer on the bottom resist layer;
forming a top resist layer on the middle resist layer;
exposing the bottom resist layer, the middle resist layer, and the top resist layer with e-beam irradiation in the area of the mask opening; and
applying one or more e-beam resist developing processes to form the mask opening in the patterned multi-layer resist stack.
12. The method of claim 11 , where covering the semiconductor substrate with a plurality of dielectric layers comprises sequentially depositing a bottom aluminum oxide layer on the gallium nitride surface layer, a middle silicon nitride layer on the bottom aluminum oxide layer, and a top aluminum oxide layer on the middle silicon nitride layer.