Scan flip-flop
View Patent ↗A scan flip-flop includes a multiplexer, a flip-flop, and a logic circuit. The flip-flop includes a transmission gate that has two sets of clock-controlled transistors. The combined width of the clock-controlled transistors in a set equals the width of the single transistor commonly used in known scan flip-flop circuits. The logic circuit inhibits the clock signal from reaching one transistor of each set during scan mode, which reduces power consumption without sacrificing speed of operation.
1. A scan flip-flop, comprising:
a multiplexer;
a flip-flop having an input connected to an output of the multiplexer; and
a logic circuit,
wherein the flip-flop includes a transmission gate for transferring a signal from the input of the flip-flop to an output of the scan flip-flop,
wherein the transmission gate includes first and second sets of switches, the first and second sets including respective first and second clock-controlled switches, wherein the first and second clock-controlled switches are connected in parallel with one another, and wherein each of the first and second sets of switches includes a first switch and a second switch, and
wherein the logic circuit, in a first mode of operation, enables clock signals for reception by the first and second switches of the first and second sets of switches of the transmission gate, and in a second mode of operation, inhibits the clock signals from reaching the first and second clock-controlled switches of the first and second sets of switches of the transmission gate.
2. The scan flip-flop of claim 1 , wherein the first set of switches comprises:
the first clock controlled switch having a gate that receives an inverse of a clock signal (/CK), a source, and a drain;
a first switch having a gate that receives a first output (A) of the logic circuit, and a drain connected to the drain of the first clock controlled switch; and
a second switch having a gate that receives a scan enable (SE) signal, a drain connected to a source of the first switch, and a source connected to the source of the clock controlled switch.
3. The scan flip-flop of claim 2 , wherein the second set of switches comprises:
the second clock-controlled switch having a gate that receives the clock signal (CK), a source connected to the source of the first clock-controlled switch at a common source node, and a drain connected to the drain of the first clock-controlled switch at a common drain node;
a third switch having a gate that receives a second output (B) of the logic circuit, and a drain connected to the common drain node; and
a fourth switch having a gate that receives an inverted version of the scan enable (SE) signal, a drain connected to the source of the third switch, and a source connected to the common source node.
4. The scan flip-flop of claim 3 , wherein the first set of switches comprise p-channel MOSFETs (metal oxide semiconductor field effect transistor) and the second set of switches comprise n-channel MOSFETs (metal oxide semiconductor field effect transistor).
5. The scan flip-flop of claim 3 , wherein the first and second clock-controlled switches each have a same width, W 1 , and the first and third switches each have a same width W 2 .
6. The scan flip-flop of claim 5 , wherein width W 1 is equal to width W 2 .
7. The scan flip-flop of claim 5 , wherein width W 1 is less than width W 2 .
8. The scan flip-flop of claim 1 , wherein the multiplexer includes a clock gating circuit comprising:
first and second pairs of clock-controlled switches for transferring one of two inputs received by the multiplexer to the multiplexer output, the first pair of clock-controlled switches being connected in series with the second pair of clock-controlled switches,
wherein each pair of clock-controlled switches of the clock gating circuit comprises third and fourth switches connected in parallel with one another, and
wherein the logic circuit, in the first mode of operation, enables the clock signals for reception by both of the third and fourth switches of each pair of clock-controlled switches of the clock gating circuit, and in a second mode of operation, inhibits the clock signals from reaching the fourth switch of each pair of clock-controlled switches of the clock gating circuit.
9. The scan flip-flop of claim 8 , wherein first pair of clock-controlled switches comprises:
a third switch having a gate that receives the clock signal (CK); and
a fourth switch having a gate that receives a second output (B) of the logic circuit, a source connected to a source of the third switch, and a drain connected to a drain of the third switch.
10. The scan flip-flop of claim 9 , wherein second pair of clock-controlled transistors comprises:
a fifth switch having a gate that receives the inverse clock signal (/CK); and
a sixth transistors having a gate that receives a first output (A) of the logic circuit, a drain connected to a drain of the fifth switch, and a source connected to a source of the fifth switch.
11. The scan flip-flop of claim 10 , wherein the third and fourth switches are PMOSFETs and the fifth and sixth transistors are NMOSFETs.
12. The scan flip-flop of claim 11 , wherein widths W 1 of the third and fifth transistors are the same as one another and wherein widths W 2 of the fourth and sixth transistors are the same as one another.
13. The scan flip-flop of claim 12 , wherein width W 1 is equal to width W 2 .
14. The scan flip-flop of claim 1 , wherein the logic circuit comprises a NOR gate having inputs for receiving a clock signal (CK) and a scan enable signal (SE), and an inverter having an input connected to an output of the NOR gate.
15. A scan flip-flop that has a data input (D), a scan data input (SI), a scan enable (SE) input, a clock signal (CK), and an output (Q), the scan flip-flop comprising:
a multiplexer;
a flip-flop having an input connected to an output of the multiplexer and an output that provides the output Q; and
a logic circuit that gates the clock signal (CK) with the scan enable (SE) to generate a first output signal (A) and a second output signal (B),
wherein the multiplexer includes:
a clock gating circuit that comprises first and second pairs of transistors, wherein the first pair of transistors comprises:
a first PMOSFET (p-channel metal oxide semiconductor) having a gate that receives the clock signal (CK), and
a second PMOSFET having a gate that receives the second output signal (B) from the logic circuit,
wherein source terminals of the first and second PMOSFETs are connected to one another at a first common source node and drain terminals of the first and second PMOSFETs are connected to each other and the output of the multiplexer, and wherein the first common source node receives either the data input (D) or the scan data input (SI) as determined by the scan enable signal (SE) and its inverse (/SE), and
the second pair of transistors comprises:
a first NMOSFET (n-channel metal oxide semiconductor) having a gate that receives an inverted version of the clock signal (/CK), and
a second NMOSFET having a gate that receives the first output signal (A) from the logic circuit,
wherein source terminals of each of the first and second NMOSFETs are connected to one another at a second common source node, and drain terminals of the first and second NMOSFETs are connected to each other and to the output of the multiplexer, and wherein the second common source node receives either the data input (D) or the scan data input (SI) as determined by the scan enable signal (SE) and its inverse (/SE).
16. The scan flip-flop of claim 15 , wherein widths W 1 of the first PMOSFET and the first NMOSFET are the same as one another and wherein widths W 2 of the second PMOSFET and the second NMOSFET are the same as one another.
17. The scan flip-flop of claim 16 , wherein width W 1 is equal to width W 2 .
18. The scan flip-flop of claim 16 , wherein a sum of the two widths (W 1 +W 2 ) equals a width of a PMOSFET of a gating circuit of a conventional scan flip-flop.
19. The scan flip-flop of claim 15 , wherein when the scan enable (SE) is low, the logic circuit output A has a value of an inverted clock signal (/CK) and the logic circuit output B has a value of the clock signal (CK), and when the scan enable (SE) is high, the output A is low and the output B is high.
20. The scan flip-flop of claim 19 , wherein the logic circuit comprises:
a NOR gate that receives as inputs the clock signal (CK) and the scan enable (SE) signal and generates the A output signal; and
an inverter connected to an output of the NOR gate 204 and that generates the B output signal.
21. An integrated circuit including a scan flip-flop, wherein the scan flip-flop comprises:
a multiplexer that receives a data input (D), a scan data input (SI), a scan enable signal (SE), a clock signal (CK) and an inverted version of the clock signal (/CK);
a flip-flop having an input connected to an output of the multiplexer; and
a logic circuit that gates the clock signal (CK) with the scan enable signal (SE) and generates a first output (A) and a second output (B) that is an inverted version of the first output (A),
wherein the flip-flop includes a clock-controlled transmission gate for transferring a signal from the input of the flip-flop to an output of the scan flip-flop, and wherein the transmission gate includes first and second sets of transistors,
wherein the first set of transistors comprises:
a first PMOSFET (p-channel metal oxide semiconductor field effect transistor) having a gate that receives the scan enable signal (SE);
a second PMOSFET having a gate that receives the first output (A) from the logic circuit, and a source connected to a drain of the first PMOSFET; and
a third PMOSFET having a gate that receives the inverted clock signal (/CK), a source connected to the source of the first PMOSFET at a common source node, and a drain connected to the drain of the second PMOSFET at a common drain node;
wherein the second set of transistors comprises:
a first NMOSFET (n-channel metal oxide semiconductor field effect transistor) having a gate that receives an inverted version of the scan enable signal (/SE), and a sourced connected to the common source node;
a second NMOSFET having a gate that receives the second output (B) from the logic circuit, a source connected to a drain of the first NMOSFET, and a drain connected to the common drain node; and
a third NMOSFET having a gate that receives the clock signal (CK), a source connected to the source of the third PMOSFET at the common source node, and a drain connected to the drain of the third PMOSFET at the common drain node; and
wherein the multiplexer includes a clock gating circuit comprising first and second pairs transistors,
wherein the first pair of transistors comprises:
a fourth PMOSFET having a gate that receives the clock signal (CK); and
a fifth PMOSFET having a gate that receives the second output signal (B) from the logic circuit, a sourced connected to the source of the fourth PMOSFET, and a drain connected to the drain of the fourth PMOSFET; and
wherein the second pair of transistors comprises:
a fourth NMOSFET having a gate that receives the inverted clock signal (/CK); and
a fifth NMOSFET having a gate that receives the first output (A) from the logic circuit, a source connected to the source of the fourth NMOSFET, and a drain connected to the drain of the fourth NMOSFET.