Memory with redundancy
View Patent ↗Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.
1. A first array comprising:
a plurality of word lines;
for each of the plurality of word lines:
a memory operable to store a bit substitution column value, the bit substitution column value associated with a bit substitution column in a second array, the bit substitution column including a bit to be substituted, the bit corresponding to a failure detected by reducing a voltage applied to the first array; and
a first data output line operable to communicate the bit substitution column value to a write column redundancy multiplexer, wherein the write column redundancy multiplexer is operable to substitute the bit by writing first data to a redundancy column in the first array in response to a first control signal from a redundancy assist circuit coupled to the first array, the redundancy assist circuit to generate the first control signal in response to the failure being detected, the write column redundancy multiplexer to the first data to a first column in the first array in response to a second control signal from the redundancy assist circuit the redundancy assist circuit to generate the second control signal in response to the failure not being detected.
2. The first array of claim 1 , wherein the first data output line is further operable to communicate the bit substitution column value to a read column redundancy multiplexer, the read column redundancy multiplexer operable to substitute the bit by reading the first data from the redundancy column in the first array based on a third control signal from the redundancy assist circuit.
3. The first array of claim 1 , wherein the first data output line is further operable to communicate the bit substitution column value to a decoder, the decoder operable to decode the bit substitution column value.
4. The first array of claim 1 , wherein the first and second arrays are subarrays of a larger third array.
5. The first array of claim 1 , wherein the first and second arrays are located remote from one another.
6. The first array of claim 2 , further comprising for each of the plurality of word lines, a second data output line operable to communicate a valid address value.
7. The first array of claim 6 , wherein the second data output line is operable to communicate the valid address value to the write column redundancy multiplexer and the read column redundancy multiplexer.
8. The first array of claim 1 , wherein reducing a voltage applied to the first array includes reducing the voltage below a minimum operating voltage of the first array.
9. The first array of claim 1 , wherein the bit substitution column value is stored in the memory as part of an automatic built-in self test process.
10. The first array of claim 1 , wherein the bit substitution column value is stored in the memory as part of an initialization process.
11. The first array of claim 1 , wherein the first array further comprises an enablement line, the enablement line operable to selectively power a portion of the first array.
12. The first array of claim 1 , wherein the first array operates at a speed faster than the speed at which the second array operates such that an access penalty associated with the first array may be less than an access time associated with the second array.
13. The first array of claim 1 , further comprising for each of the plurality of word lines:
a second memory operable to store a second bit substitution column value, the second bit substitution column value;
a second data output line operable to communicate the second bit substitution column value to the write column redundancy multiplexer, wherein the write column redundancy multiplexer is operable to substitute a second bit by writing second data to the first column in the first array based on the first control signal, the write column redundancy multiplexer to write the second data to a second column in the first array in response the second control signal from the redundancy assist circuit; and
a write column redundancy multiplexer select line operable to communicate a write column redundancy multiplexer select value of the first control signal to the write column redundancy multiplexer.
14. The first array of claim 13 , further comprising for each of the plurality of word lines:
the second data output line is further operable to communicate the second bit substitution column value to the read column redundancy multiplexer, wherein the read column redundancy multiplexer is operable to substitute the second bit by reading the second data from the first column based on the third control signal; and
a read column redundancy multiplexer select line operable to communicate a read column redundancy multiplexer select value of the third control signal to the read column redundancy multiplexer.
15. The first array of claim 1 , wherein the first array comprises nonvolatile memory.
16. A system for implementing data redundancy, the system comprising:
a memory array comprising:
a plurality of word lines;
a bit substitution column including a bit to be substituted, the bit corresponding to a failure detected by reducing a voltage applied to the memory array; and
a redundancy column;
a read column redundancy multiplexer coupled to the memory array;
a write column redundancy multiplexer coupled to the memory array; and
a programmable assist array coupled to the plurality of word lines and comprising, for each of the plurality of word lines:
a memory operable to store a bit substitution column value associated with the bit substitution column;
a first data output line operable to communicate the bit substitution column value to the read column redundancy multiplexer and the write column redundancy multiplexer; and
a second data output line operable to communicate a valid address value to the read column redundancy multiplexer and the write column redundancy multiplexer, wherein:
the write column redundancy multiplexer is operable to substitute the bit by writing first data to the redundancy column in response to a first control signal corresponding to the bit substitution column value and a valid address value, the redundancy assist circuit to generate the first control signal in response to the failure being detected, the write column redundancy multiplexer to write the first data to a first column in the first array in response to a second control signal from the redundancy assist circuit, the redundancy assist circuit to generate the second control signal in response to the failure not being detected; and
the read column redundancy multiplexer is operable to substitute the bit by reading data from the redundancy column in response to a third control signal corresponding to the bit substitution column value and the valid address value.
17. The system of claim 16 further comprising a decoder coupled to the programmable assist array and the read column redundancy multiplexer, the decoder operable to decode the bit substitution column value.
18. The system of claim 16 further comprising a decoder coupled to the programmable assist array and the write column redundancy multiplexer, the decoder operable to decode the bit substitution column value.
19. A system for implementing redundancy, the system comprising:
a memory array comprising:
a first plurality of word lines responsive to a row address;
a bit substitution column including a bit to be substituted, the bit corresponding to a failure detected by reducing a voltage applied to the memory array; and
a redundancy column;
a read column redundancy multiplexer coupled to the memory array;
a write column redundancy multiplexer coupled to the memory array; and
a programmable assist array comprising a second plurality of word lines responsive to the row address, wherein for each of the second plurality of word lines, the programmable assist array comprises:
a memory operable to store a bit substitution column value associated with the bit substitution column;
a first data output line operable to communicate the bit substitution column value to the read column redundancy multiplexer and the write column redundancy multiplexer; and
a second data output line operable to communicate a valid address value to the read column redundancy multiplexer and the write column redundancy multiplexer, wherein:
the write column redundancy multiplexer is operable to substitute the bit by writing data to the redundancy column in response to a first control signal corresponding to the bit substitution column value and a valid address value, the redundancy assist circuit to generate the first control signal in response to the failure being detected, the write column redundancy multiplexer to write the first data to a first column in the first array in response to a second control signal from the redundancy assist circuit the redundancy assist circuit to generate the second control signal in response to the failure not being detected; and
the read column redundancy multiplexer is operable to substitute the bit by reading the first data from the redundancy column in response to a third control signal corresponding to the bit substitution column value and the valid address value.
20. The system of claim 19 further comprising a decoder coupled to the programmable assist array, the decoder operable to decode the bit substitution column value.