Synchronization circuitry, common public radio interface enable device, and a method of synchronizing a synchronized clock signal of a second transceiver to a clock of a first transceiver
View Patent ↗A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. The synchronization circuitry comprises a clock input port for receiving an external clock signal from an external clock generator. At a received signal input port the received signal can be received from the master transceiver. A tracking loop couples the received signal input and the second phase input to a control input of a controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase and or frequency error between the external clock signal and the received signal.
1. A controller device for a data interface between a slave sub-system and a master sub-system in a chain of at least two sub-systems in a mobile communication base station system, each of the sub-systems comprising at least one slave sub-system and at least one master sub-system for controlling the time of the slave sub-system, the at least one master sub-systems comprising a synchronization master sub-system controlling a time synchronization of the chain to an external clock external to the chain, the controller device comprising:
a slave transceiver, for receiving a received signal representing binary data from a master sub-system, the binary data having a bit duration controlled by a clock cycle of a transmit clock of the master sub-system, and the transmitting data to the master sub-system, the transceiver being connected with a clock input to a controllable phase locked loop, PLL, for clocking the transceiver with the transmit clock; and
a synchronization device for synchronizing the transmit clock of the slave transceiver to a clock of a master transceiver of the master sub-system based on the received signal received from the master sub-system, the synchronization circuitry comprising:
a clock input port for receiving an external clock signal from an external clock generator;
a received signal input port for receiving the received signal from the master transceiver;
said PLL, for generating the transmit clock, the PLL comprising a PLL output for outputting the transmit clock, a first phase input coupled to the clock input port and a second phase input coupled to the PLL output via a negative feedback loop for providing a negative feedback signal; and
a frequency and phase tracking loop coupling the received signal input and the second phase input, for providing a selection signal which controls a phase and/or frequency of the negative feedback signal to counter phase and or frequency error between the external clock signal and the received signal,
wherein the frequency and phase tracking loop comprises:
a clock recovery circuit for generating a receiver clock signal on basis of the transmit clock signal and the received signal,
a phase detector circuit for generating a phase error signal, the phase detector circuit receiving the negative feedback signal and the receiver clock signal of which the frequency is divided by a first factor, the phase error signal indicating a phase difference between the negative feedback signal and the divided receiver clock signal,
a selection signal generator for generating the selection signal on basis of the phase error signal, to select the selected clock signal, wherein the selection signal generator comprises an integrator and counter circuit for generating the selection signal.
2. The controller device as claimed in claim 1 , wherein the PLL comprises:
a frequency multiplying circuit for generating a plurality of clock signals each having a different phase and having a frequency that is a first factor higher than a frequency of the external clock signal, a first one of the plurality of clock signals being selected as the transmit clock signal; and
the negative feedback loop comprising a configurable dividing circuit for generating the negative feedback signal from at least one selected clock signal out of the plurality of clock signals.
3. The controller device according to claim 1 , wherein the configurable dividing circuitry comprises a selection circuit and a first frequency divider, the selection circuit arranged to dynamically select a selected one of the plurality of clock signals from the plurality of clock signals in dependence on the selection signal, the first frequency divider is arranged to generate the negative feedback signal by dividing the frequency of the selected one of the plurality of clock signals by the first factor.
4. The controller device according to claim 1 , wherein the integrator and counter circuit is configured to generate the selection signal on basis of calculating the change in phase.
5. The controller device according to claim 1 , wherein the selection signal generator comprises a mux controller circuit for selecting the selected clock signal.
6. The controller device according to claim 1 further comprising a second frequency divider, the second frequency divider is provided in between an output of the clock recovery circuit and an input of the phase detector circuit for dividing the frequency of the receiver clock signal by the first factor.
7. The controller device according to claim 1 , wherein a frequency of the received signal is a selected one of a plurality of predefined allowed frequencies and the master sub-system and slave sub-system are configured to send and receive data at different speeds.
8. The controller device according to claim 7 , wherein the first factor is a configurable factor in dependence of the frequency of the received signal.
9. The controller device according to claim 4 , wherein the integrator and counter circuit is configurable in dependence of the frequency of the received signal, wherein parameters of the change in phase are configured in dependence of the frequency of the received signal.
10. The controller device according to claim 1 , wherein the interface is compliant or compatible with common public radio interface standard version 1 or higher.
11. An integrated circuit comprising the device according to claim 1 .
12. A RF or baseband sub-system for a base station in a mobile communication system, comprising the controller device according to claim 1 .
13. A mobile communications base station system, comprising at least one chain of at least two sub-systems, the sub-systems comprising at least one slave sub-system and at least one master sub-system for controlling the second sub-system, at least one first sub-systems being a synchronization master controlling time in the chain, wherein at least one of the master systems is a baseband subsystem, at least one of the slave subsystem is a radio frequency subsystem and at least one of the slave subsystems is an RF or baseband sub-system as claimed in claim 12 .
14. A method of synchronizing a synchronized clock signal of a second transceiver to a clock of a first transceiver based on a received signal, the method comprising:
receiving an external clock signal from an external clock generator and providing the external clock signal to a first input of a phase locked loop circuit,
receiving the received signal that is transmitted by the first transceiver,
generating in the phase locked loop circuit a plurality of clock signals having a frequency that is a first factor higher than a frequency of the external clock signal, all clock signals of the plurality of clock signals have a different phase,
providing the synchronized clock signal, the synchronized clock signal being a first one of the plurality of clock signals,
generating a feedback signal in a configurable dividing circuitry in dependence of a selection signal and on basis of the plurality of clock signals,
providing the feedback signal to a second input of the phase locked loop circuit,
recovering a receiver clock signal from the received signal and the synchronized clock signal in a clock recovery circuit,
obtaining a frequency divided receiver clock signal from the receiver clock signal by dividing a frequency of the receiver clock signal by the first factor,
detecting a phase error between the feedback signal and the frequency divided receiver clock signal,
generating a phase error signal based on the detected phase error,
generating in a selection signal generator comprising an integrator and counter circuit the selection signal based on the phase error signal, and
using the selection signal to select one of the plurality of clock signals.
15. The method according to claim 14 , wherein a frequency of the received signal may be a selected one of a plurality of predefined allowed frequencies and the method further comprises the stage of adapting the first factor in dependence of the frequency of the received signal.
16. The method according to claim 15 , in generating a phase error signal comprises calculating a change in phase of detected phase errors and wherein parameters of the change in phase are adapted to the frequency of the received signal.