Granted Patent B2

US 9,330,216 · App. 14/320,589 · Granted May 3, 2016

Abstract

Claims (34)

1. A method for designing an integrated circuit (IC), the method comprising:

generating a current design for the IC using a computer system;

generating a current slack histogram for the current design using the computer system; and

generating an updated design for the IC by applying a histogram-based algorithm to the current design based on the current slack histogram, using the computer system,

wherein the histogram-based algorithm comprises a worst negative slack (WNS) optimization followed by a total negative slack (TNS) optimization.

2. The method of claim 1 , wherein the updated design has a TNS having a smaller magnitude than the TNS of the current design.

3. The method of claim 1 , further comprising fabricating the IC based on the updated design.

4. The method of claim 1 , wherein the WNS optimization comprises:

designating a bin in the current slack histogram corresponding to top failing paths in the current design as the peak of a first Gaussian distribution in the current slack histogram;

designating a bin in the current slack histogram corresponding to a next significant peak in the current slack histogram as the peak of a second Gaussian distribution in the current slack histogram;

dividing the portion of the current slack histogram between the peaks of the first and second Gaussian distributions into a plurality of different cost groups, wherein the top failing paths in the current design are assigned to a top cost group of the plurality of different cost groups;

assigning a weight value to each cost group of the plurality of different cost groups; and

applying incremental timing optimization based on the cost groups and assigned weight values to generate the updated design.

5. The method of claim 4 , wherein:

a lowest weight value is assigned to the top cost group;

a highest weight value is assigned to the cost group next to the top cost group; and

a lesser weight value is assigned to each successive cost group.

6. The method of claim 1 , wherein the TNS optimization comprises:

generating a TNS contribution curve from the current slack histogram;

designating a point in the TNS contribution curve corresponding to top failing paths in the current design as the peak of a first Gaussian distribution in the TNS contribution curve;

designating a point in the TNS contribution curve corresponding to a next significant peak in the TNS contribution curve as the peak of a second Gaussian distribution in the TNS contribution curve;

dividing the portion of the TNS contribution curve between the peaks of the first and second Gaussian distributions into a plurality of different cost groups, wherein the top failing paths in the current design are assigned to a top cost group of the plurality of different costs groups;

assigning a weight value to each cost group of the plurality of different cost groups; and

applying incremental timing optimization based on cost groups and assigned weight values to generate the updated design.

7. The method of claim 1 , wherein generating an updated design comprises:

applying WNS optimization to the current design based on the current slack histogram to generate an invalid, intermediate design for the IC;

generating an intermediate slack histogram for the intermediate design; and

applying TNS optimization to the intermediate design based on the intermediate slack histogram to generate the updated design.

8. The method of claim 1 , further comprising:

updating at least one of timing constraints and design constraints for the updated design to generate a further updated design;

performing technology mapping on the further updated design;

determining whether the further updated design satisfies timing requirements for the IC; and

repeating generating an updated design, updating at least one of timing constraints, technology mapping, and determining if the further updated design does not satisfy the timing requirements for the IC.

9. The method of claim 8 , wherein generating an updated design, updating at least one of timing constraints, technology mapping, and determining are repeated until the further updated design does satisfy the timing requirements for the IC.

Assignments (16)