LDMOS minority carrier shunting
View Patent ↗A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.
1. A device comprising:
a semiconductor substrate;
source and drain regions in the semiconductor substrate and having a first conductivity type;
a gate structure supported by the semiconductor substrate between the source and drain regions;
a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation; and
a second well region adjacent to the first well region, having the second conductivity type, having a deeper bottom boundary than the first well region, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region;
wherein the second well region is configured to lower an effective base resistance of the parasitic bipolar transistor having the first well region as a base region.
2. The device of claim 1 , wherein the second well region is disposed under the source region such that the path extends under the source region.
3. The device of claim 1 , wherein the second well region does not extend under the gate structure.
4. The device of claim 1 , wherein the second well region is aligned with a source-side of the gate structure.
5. The device of claim 1 , wherein the second well region is spaced from a source-side corner of the gate structure.
6. The device of claim 1 , further comprising a sinker region in the semiconductor substrate, having the second conductivity type, and disposed in the semiconductor substrate to further carry the charge carriers along the path.
7. The device of claim 1 , further comprising:
a contact disposed on a backside of the semiconductor substrate; and
a sinker region in the semiconductor substrate, having the second conductivity type, and configured to establish an electrical connection between the source region and the backside contact;
wherein the second well region is adjacent the sinker region such that the path is electrically coupled to the backside contact.
8. The device of claim 1 , wherein the second well region is laterally spaced from a source-side edge of the gate structure.
9. The device of claim 1 , wherein the path is laterally oriented.
10. The device of claim 1 , further comprising a drift region in the semiconductor substrate between the first well region and the drain region and having the first conductivity type to allow charge carriers of the first conductivity type in the channel region to reach the drain region.
11. An electronic apparatus comprising:
a substrate; and
a transistor disposed in the substrate, the transistor comprising:
first and second semiconductor regions having a first conductivity type;
a third semiconductor region having a second conductivity type and in which a channel region is formed between the first and second semiconductor regions during operation;
a fourth semiconductor region adjacent to the third semiconductor region, having the second conductivity type, having a deeper bottom boundary than the third semiconductor region, and having a higher dopant concentration than the third semiconductor region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the first semiconductor region; and
a drift region in the semiconductor substrate between the third semiconductor region and the second semiconductor region and having the first conductivity type to allow charge carriers of the first conductivity type in the third semiconductor region to reach the second semiconductor region.
12. The electronic apparatus of claim 11 , further comprising a sinker region in the semiconductor substrate, having the second conductivity type, and disposed along the path.
13. The electronic apparatus of claim 11 , wherein the fourth semiconductor region does not extend under the channel region.
14. The electronic apparatus of claim 11 , wherein the fourth semiconductor region extends under the first semiconductor region such that the path extends under the first semiconductor region.
15. A method of fabricating a transistor, the method comprising:
forming a gate structure of the transistor on a semiconductor substrate;
forming a first well region in the semiconductor substrate, the first well region extending under the gate structure where a channel region is formed during operation;
forming a second well region in the semiconductor substrate adjacent the first well region and having a deeper bottom boundary than the first well region; and
forming a source region in the semiconductor substrate such that the second well region is under the source region;
wherein the second well region has a higher dopant concentration than the first well region to establish a path to carry minority charge carriers away from a parasitic bipolar transistor involving a junction between the channel region and the source region, and
wherein forming the second well region comprises conducting an implantation of dopant that uses the gate structure as a mask.
16. The method of claim 15 , further comprising forming a sinker region in the semiconductor substrate in a position to further carry the charge carriers along the path.
17. The method of claim 15 , wherein forming the gate structure comprises depositing a spacer such that the gate structure comprises the spacer.
18. The method of claim 15 , wherein forming the gate structure comprises depositing a spacer along a source-side sidewall of the gate structure such that a vertical boundary of the second well region formed via the implantation is laterally spaced from the source-side sidewall.
19. The method of claim 15 , wherein the implantation of dopant is conducted at an angle with respect to vertical to laterally space the second well region from a source-side corner of the gate structure.
20. A device comprising:
a semiconductor substrate;
source and drain regions in the semiconductor substrate and having a first conductivity type;
a gate structure supported by the semiconductor substrate between the source and drain regions;
a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation;
a second well region adjacent to the first well region, having the second conductivity type, having a deeper bottom boundary than the first well region, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region;
a contact disposed on a backside of the semiconductor substrate; and
a sinker region in the semiconductor substrate, having the second conductivity type, and configured to establish an electrical connection between the source region and the backside contact;
wherein the second well region is adjacent the sinker region such that the path is electrically coupled to the backside contact.
21. A method of fabricating a transistor, the method comprising:
forming a gate structure of the transistor on a semiconductor substrate;
forming a first well region in the semiconductor substrate, the first well region extending under the gate structure where a channel region is formed during operation;
forming a second well region in the semiconductor substrate adjacent the first well region and having a deeper bottom boundary than the first well region; and
forming a source region in the semiconductor substrate such that the second well region is under the source region;
wherein the second well region has a higher dopant concentration than the first well region to establish a path to carry minority charge carriers away from a parasitic bipolar transistor involving a junction between the channel region and the source region, and
wherein forming the gate structure comprises depositing a spacer along a source-side sidewall of the gate structure such that a vertical boundary of the second well region formed via the implantation is laterally spaced from the source-side sidewall.
22. A method of fabricating a transistor, the method comprising:
forming a gate structure of the transistor on a semiconductor substrate;
forming a first well region in the semiconductor substrate, the first well region extending under the gate structure where a channel region is formed during operation;
forming a second well region in the semiconductor substrate adjacent the first well region and having a deeper bottom boundary than the first well region; and
forming a source region in the semiconductor substrate such that the second well region is under the source region;
wherein the second well region has a higher dopant concentration than the first well region to establish a path to carry minority charge carriers away from a parasitic bipolar transistor involving a junction between the channel region and the source region, and
wherein the implantation of dopant is conducted at an angle with respect to vertical to laterally space the second well region from a source-side corner of the gate structure.