Granted Patent B2

US 9,379,222 · App. 14/291,320 · Granted Jun 28, 2016

Abstract

Claims (74)

1. A method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) structure in an NVM region of the semiconductor structure, the method comprising:

forming a dummy select gate structure including a first material on the substrate;

forming a dummy control gate structure including a second material on the substrate, wherein

the first material is different from the second material;

replacing the dummy select gate structure with a metal select gate structure, wherein

the replacing the dummy select gate structure comprises

removing the dummy select gate structure without removing the dummy control gate structure; and

replacing the dummy control gate structure with a polysilicon control gate structure, wherein

the replacing the dummy control gate structure comprises

removing the dummy control gate structure without removing the metal select gate structure.

2. The method of claim 1 , wherein

the replacing the dummy select gate structure comprises

etching the first material included in the dummy select gate structure using an etchant to leave an opening, wherein

the etchant substantially removes the first material, and

the etchant does not substantially remove the second material included in the dummy control gate structure.

3. The method of claim 2 , wherein

the replacing the dummy select gate structure further comprises

forming a metal gate stack in the opening to form the metal select gate structure.

4. The method of claim 1 , wherein

the replacing the dummy control gate structure comprises

etching the second material included in the dummy control gate structure using an etchant to leave an opening, wherein

the etchant substantially removes the second material, and

the etchant does not substantially remove the third material included in the metal select gate structure.

5. The method of claim 4 , wherein

the third material forms a capping layer on the metal select gate structure.

6. The method of claim 4 , wherein

the replacing the dummy control gate structure further comprises

forming a polysilicon gate stack in the opening to form the polysilicon control gate structure.

7. The method of claim 1 , wherein

the forming the dummy select gate structure and the forming the dummy control gate structure comprises

forming a charge storage layer over the substrate including over a first portion of the first material and along a side of the first portion,

forming a second layer of the second material over the charge storage layer, and

etching the second layer and the charge storage layer to form the dummy select gate structure and the dummy control gate structure.

8. The method of claim 1 , further comprising

prior to the replacing the dummy select gate structure and the replacing the dummy control gate structure,

forming an interlayer dielectric (ILD) layer over the substrate including over the dummy select gate structure and the dummy control gate structure, and

performing chemical mechanical polishing on the NVM region to reveal a top first surface of the first material and a second top surface of the second material.

9. The method of claim 1 , wherein

an etchant utilized in one of the replacing the dummy select gate structure and the replacing the dummy control gate structure does not substantially remove oxide and an interlayer dielectric (ILD) material.

10. The method of claim 1 , wherein

the dummy control gate structure is a spacer structure.

11. A method of making a split gate non-volatile memory (NVM) structure using a semiconductor substrate, the method comprising:

etching a first dummy material included in a dummy select gate stack formed on the semiconductor substrate to form a first opening, wherein

the etching the first dummy material does not substantially remove a second dummy material included in a dummy control gate stack formed on the semiconductor substrate, and

the first dummy material is different from the second dummy material;

forming a metal select gate stack in the first opening;

etching the second dummy material to form a second opening, wherein

the etching the second dummy material does not substantially remove a third material included in the metal select gate stack; and

forming a polysilicon control gate stack in the second opening.

12. The method of claim 11 , further comprising

forming the dummy select gate stack and the dummy control gate stack, comprising:

etching a first layer of the first dummy material formed over the semiconductor substrate to form at least a first side of the dummy select gate stack,

forming a charge storage layer over the semiconductor substrate including along the first side of the dummy select gate stack,

forming a second layer of the second dummy material over the charge storage layer, and

etching the second layer and the charge storage layer to form the dummy control gate stack and a second side of the dummy select gate stack.

13. The method of claim 12 , wherein

the etching the second layer and the charge storage layer further comprises

etching the first layer to form the second side of the dummy select gate stack.

14. The method of claim 13 , further comprising

prior to the etching the first layer and the etching the second layer and the charge storage layer,

forming an interlayer dielectric (ILD) layer over the semiconductor substrate including over the dummy select gate stack and the dummy control gate stack.

15. The method of claim 13 , further comprising

prior to the etching the first layer and the etching the second layer and the charge storage layer,

performing chemical mechanical polishing on the semiconductor substrate to reveal a first top surface of the first dummy material included in the dummy select gate stack and a second top surface of the second dummy material included in the dummy control gate stack.

16. The method of claim 15 , wherein

the chemical mechanical polishing removes an upper portion of the dummy select gate stack and of the dummy control gate stack.

17. The method of claim 12 , further comprising

forming sidewall spacers along the second side of the dummy select gate stack and a third side of the dummy control gate stack.

18. The method of claim 12 , wherein

the etching the second layer and the charge storage layer comprises

performing a spacer etch on the second layer to form the dummy control gate stack, wherein

the dummy control gate stack is a spacer structure.

19. The method of claim 11 , wherein

the third material forms a capping layer on the metal select gate stack.

Assignments (16)