IP Library Granted Patent US 9,329,932
Granted Patent B2
US 9,329,932 · App. 14/262,116 · Granted May 3, 2016

Imminent read failure detection based upon unacceptable wear for NVM cells

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Quick Facts
Patent No.
US 9,329,932
App. No.
14/262,116
Granted
May 3, 2016
Kind
B2
Abstract

Methods and systems are disclosed for imminent read failure detection based upon unacceptable wear for non-volatile memory (NVM) cells. In certain embodiments, a first failure time is recorded when a first diagnostic mode detects an uncorrectable error within the NVM cell array using a first set of read voltage levels below and above a normal read voltage level. A second failure time is recorded when a second diagnostic mode detects an uncorrectable error within the NVM cell array using a second set of read voltage levels below and above a normal read voltage level. The first and second failure times are then compared against a threshold wear time value to determine whether or not an imminent read failure is indicated. The diagnostic modes can be run separately for erased NVM cell distributions and programmed NVM cell distributions to provide separate wear rate determinations.

Claims (30)

1. A method for detecting imminent read failures for a non-volatile memory (NVM) system, comprising:

periodically performing read operations for a first diagnostic mode for an array of non-volatile memory (NVM) cells until a first uncorrectable read error is detected at a first time;

periodically performing read operations for a second diagnostic read mode for the array of NVM cells until a second uncorrectable read error is detected at a second time;

comparing a difference between the second time and the first time with a threshold time value; and

indicating an imminent read failure for the array of NVM cells based upon the comparison.

2. The method of claim 1 , wherein the first diagnostic mode uses a first low voltage read level less than a normal read voltage level and uses a first high voltage read level greater than the normal read voltage level, the normal read voltage level being used for non-diagnostic read operations for the array of NVM cells.

3. The method of claim 2 , wherein the first low voltage read level is between 0.6 to 1.0 volts below the normal read voltage level, and wherein the first high voltage read level is between 0.6 to 1.5 volts above the normal read voltage level.

4. The method of claim 2 , wherein the second diagnostic mode uses a second low voltage read level less than the normal read voltage level and greater than the first low voltage read level and uses a second high voltage read level greater than the normal read voltage level and less than the first high voltage read level.

5. The method of claim 4 , wherein the second low voltage read level is between 0.3 to 0.6 volts below the normal voltage level, and wherein the second high voltage read level is between 0.3 to 0.6 volts above the normal voltage level.

6. The method of claim 4 , wherein the periodically performing, comparing, and indicating steps are performed using the low voltage read levels for erased cells within the array of NVM cells and are performed using the high voltage read levels for programmed cells within the array of NVM cells.

7. The method of claim 1 , further comprising using one or more error correction code (ECC) routines for the periodically performing steps.

8. The method of claim 7 , wherein the error correction routines are configured to identify a double-bit error as an uncorrectable read error.

9. The method of claim 1 , wherein the indicating step comprises storing within a data storage medium a flag indicating whether or not an imminent read failure condition has been detected.

10. The method of claim 1 , wherein the indicating step comprises outputting a failure indicator signal.

11. The method of claim 1 , wherein the first time and the second time are determined using timestamps and wherein the threshold time value comprises a threshold time difference amount.

12. The method of claim 1 , wherein the first time and the second time are determined using counted values and wherein the threshold time value represents a threshold counted difference amount.

13. The method of claim 12 , wherein the counted value comprises at least one the following: power-up events for the NVM system, operational cycles for the NVM system, automobile starts for an automobile within which the NVM system is operating, or odometer readings for an automobile within which the NVM system is operating.

14. A non-volatile memory (NVM) system having imminent read failure detection, comprising:

a non-volatile memory (NVM) including an array of NVM cells;

a memory management unit coupled to the array of NVM cells;

a controller within the memory management unit coupled to the NVM and configured to perform read operations for the NVM cells;

the controller being configured to periodically perform read operations for a first diagnostic mode for the array of NVM cells until a first uncorrectable read error is detected at a first time;

the controller being further configured to periodically perform read operations for a second diagnostic read mode for the array of NVM cells until a second uncorrectable read error is detected at a second time; and

the controller being further configured to compare a difference between the second time and the first time with a threshold time value and to indicate an imminent read failure for the array of NVM cells based upon the comparison.

15. The NVM system of claim 14 , wherein the first diagnostic mode is configured to use a first low voltage read level less than a normal read voltage level and to use a first high voltage read level greater than the normal read voltage level, the normal read voltage level being used for non-diagnostic read operations for the array of NVM cells.

16. The NVM system of claim 15 , wherein the second diagnostic mode is configured to use a second low voltage read level less than the normal read voltage level and greater than the first low voltage read level and to use a second high voltage read level greater than the normal read voltage level and less than the first high voltage read level.

17. The NVM system of claim 16 , wherein the controller is configured to use the low voltage read levels to indicate imminent read failures for erased cells within the array of NVM cells and to use the high voltage read levels to indicate imminent read failures for programmed cells within the array of NVM cells.

18. The NVM system of claim 16 , further comprises a data storage medium configured to store the low voltage read levels, the high voltage read levels, and at least one threshold time value.

19. The NVM system of claim 14 , wherein the memory management unit further comprises error correction code (ECC) logic configured to run one or more ECC routines, and wherein the controller is further configured to use results from the ECC logic as indications of uncorrectable read errors.

20. The NVM system of claim 14 , wherein the controller is further configured to indicate the imminent read failure using a flag within a data storage medium or using a failure indicator output signal or both.

Assignments (16)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2014
From: WEILEMANN, JON W., II; EGUCHI, RICHARD K.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032760/0106 →